Cx Shram Configuration Register 1 (Cxsrcr1); Cx Shram Configuration Register 1 (Cxsrcr1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

RAM Control Module Registers
5.2.1.2

Cx SHRAM Configuration Register 1 (CxSRCR1)

31
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-10. Cx SHRAM Configuration Register 1 (CxSRCR1) Field Descriptions
Bit Field
31-11 Reserved
10 CPUWRPROTC3
9 DMAWRPROTC3
8 FETCHPROTC3
7-3 Reserved
2 CPUWRPROTC2
1 DMAWRPROTC2
0 FETCHPROTC2
438
Internal Memory
Figure 5-5. Cx SHRAM Configuration Register 1 (CxSRCR1)
Reserved
Reserved
R-0
Reserved
R-0
Value Description
Reserved
CPU Write Protection C3
0 M3 CPU write allowed to C3 RAM block.
1 M3 CPU write not allowed to C3 RAM block.
µDMA Write Protection C3
0 M3 µDMA write allowed to C3 RAM block.
1 M3 µDMA write not allowed to C3 RAM block.
CPU Fetch Protection C3
0 M3 CPU Fetch allowed from C3 RAM block.
1 M3 CPU Fetch not allowed from C3 RAM block.
Reserved
CPU Write Protection C2
0 M3 CPU write allowed to C2 RAM block.
1 M3 CPU write not allowed to C2 RAM block.
µDMA Write Protection C2
0 M3 µDMA write allowed to C2 RAM block.
1 M3 µDMA write not allowed to C2 RAM block.
CPU Fetch Protection C2
0 M3 CPU Fetch allowed from C2 RAM block.
1 M3 CPU Fetch not allowed from C2 RAM block.
Copyright © 2012–2019, Texas Instruments Incorporated
R-0
11 10
CPUWRPROT
C3
R/W-0
3 2
CPUWRPROT
C2
R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
16
9 8
DMAWRPROT FETCHPROTC
C3 3
R/W-0 R/W-0
1 0
DMAWRPROT FETCHPROTC
C2 2
R/W-0 R/W-0
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