Fmc Interface With Core, Bank And Pump - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Name
EMACID0
EMACID1
CUSTOMER_OPT_MAIN_OS
C_CLK_FREQ
OTP BOOTMODE GPIO
CONFIG REGISTER
5.3.5 Flash Module Controller (FMC)
There is a dedicated flash module controller in both the master subsystem (M3-FMC) and the control
subsystem (C28x-FMC). The Cortex M3 core in the master subsystem interfaces with the M3 flash module
controller (M3-FMC), which in turn, interfaces with the M3 flash bank and shared pump to perform
erase/program operations as well as to read data/execute code from the M3 flash bank.
The C28x core in the control subsystem interfaces with the C28x flash module controller (C28x-FMC)
which in turn, interfaces with the C28x flash bank and shared pump to perform erase/program operations
as well as to read data/execute code from the C28x flash bank. Control signals to the flash pump will be
controlled by either C28x-FMC or M3-FMC, depending on who gains the flash pump semaphore.
There is a state machine in both M3-FMC and C28x-FMC which generates the erase/program sequences
in hardware. This simplifies the Flash API software (refer to the C2000 F021 Application Programming
Interface (API) Reference Guide, SPNU595, for details on Flash API) which configures control registers in
FMC to perform flash erase and program operations.
The following sections
describe FMC in detail.
SPRUH22I – April 2012 – Revised November 2019
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Table 5-83. Programmable OTP Locations in M3 OTP (continued)
Address
0x680810
0x680814
0x68081C
0x680824
Figure 5-78. FMC Interface with Core, Bank and Pump
C28x System Clock
C28x Core
Cortex-M3
M3 System Clock
(Section 5.3.6, Section
Copyright © 2012–2019, Texas Instruments Incorporated
Size (x8)
4 Default EMAC ID = 0x1A:B6:00:64:00. By
programming these two OTP addresses, the
4
user can change default EMAC ID. If left
unprogrammed, default EMAC ID =
0x1A:B6:00:64:00
4 Input main osc frequency connected to the
device. Mboot ROM reads this location to know
the MAINOSC frequency to configure the bit
rate for CAN / I2C0 and SSI0 master mode /
EMAC bootloader. If left unprogrammed,the
default input main osc frequency = 20 MHz
4 Used to configure alternate boot mode pins
C28x-Bank
C28-FMC
Pump
M3-FMC
PUMP SEMAPHORE
M3-Bank
5.3.8, Section 5.3.8, Section
Flash Controller Memory Module
Description
5.3.9, and Section 5.3.10) will
Internal Memory
495