Irdy Signal Operation, Frm50 = 0, Frmcnt = 0, And Rd2Cyc = 1; Epi Clock Operation, Clkgate = 1, Wr2Cyc - Texas Instruments Concerto F28M35 Series Technical Reference Manual

General-Purpose Mode
17.8.1.2 iRDY Signal Operation
The ready input (iRDY) signal can be used to lengthen bus cycles and is enabled by the RDYEN bit in the
EPIGPCFG register. iRDY is input on EPI0S27 and may only be used with a free-running clock
(CLKGATE is clear). If iRDY is deasserted, further transactions are held off until the iRDY signal is
asserted again. iRDY is sampled on the falling edge of the EPI clock and gates transactions, no matter
what state they are in
A two-cycle access has two phases in the bus cycle. The first clock is the address phase, and the second
clock is the data phase. If iRDY is sampled Low at the start of the address phase then the address phase
is extended (FRAME, RD, and Address are all asserted) until after iRDY has been sampled High again.
Data is sampled on the subsequent rising edge.
If iRDY is sampled Low at the start of the data phase, as shown in
Address, and Data signals behave as they would during a normal transaction in T1. The data phase (T2)
is extended with only Address being asserted until iRDY is recognized as asserted again. Data is latched
on the subsequent rising edge
Figure 17-24. iRDY Signal Operation, FRM50 = 0, FRMCNT = 0, and RD2CYC = 1
Clock
(
EPI0S31
Frame
(EPI0S30)
RD
(
EPI0S29
iRDY
(
EPI0S27
Address
Data
17.8.1.3 EPI Clock Operation
If the CLKGATE bit in the EPIGPCFG register is clear, the EPI clock always toggles when General-
purpose mode is enabled. If CLKGATE is set, the clock is output only when a transaction is occurring,
otherwise the clock is held high. If the WR2CYC bit is clear, the EPI clock begins toggling 1 cycle before
the WR strobe goes high. If the WR2CYC bit is set, the EPI clock begins toggling when the WR strobe
goes high. The clock stops toggling after the first rising edge after the WR strobe is deasserted. The RD
strobe operates in the same manner as the WR strobe when the WR2CYC bit is set, as the RD2CYC bit
must always be set. See
Figure 17-25. EPI Clock Operation, CLKGATE = 1, WR2CYC = 0
(
(
1222
External Peripheral Interface (EPI)
T0 T1
)
)
)
Figure 17-25 and Figure
Clock
)
EPI0S31
WR
)
EPI0S28
Address
Data
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 17-24, the FRAME, RD,
T2 T3
17-26.
SPRUH22I – April 2012 – Revised November 2019
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