Shared Ram (Dedicated To Subsystem); Shared Ram (Shared Between Subsystems); Master Access For Sx Ram (Assuming All Other Protections Are Disabled) - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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All these RAMs have the access protection (cpu write/cpu fetch/dma write) feature. Each type of access
protection for each RAM block can be enabled/disabled by configuring the specific bit in the shared RAM
configuration registers, allocated to each subsystem (CxSRCR for the M3 subsystem and LxSRCR for the
C28x subsystem).
Another type of shared RAMs (Sx RAMs) is accessible from all the masters and used for data and code
storage (see Figure
DMA engines (C28 DMA/M3 uDMA). Each shared RAM can be owned by the M3 subsystem or the C28x
subsystem based on the configuration of respective bits (one bit for each Sx memory) in the MSxMSEL
register. When an Sx RAM block is owned by the M3 subsyteam, the M3 CPU and µDMA have full access
to that RAM block, whereas the C28x CPU and DMA have only read access to that RAM block (no
fetch/write access).
This register is only mapped to the M3 CPU, which means the master ownership setting for Sx RAMs can
be changed by software running on the M3 subsystem. This register can be LOCKED by the user to
prevent further updates to the MSxSEL register. Once it's locked, it can be unlocked only by
SharedResorceReset. The C28x subsystem has a status register, CSxMSEL, which reflects the ownership
status of each Sx RAM block (see
SxMSEL M3 Fetch
0 Yes
1 No
Like other shared RAM, these RAMs also have a different level of access protection which can be
enabled/disabled by configuring specific bits in the MSxSRCR register (when the RAM block is owned by
the M3 subsystem) or the CSxSRCR register (when the RAM block is owned by the C28x subsystem).
SPRUH22I – April 2012 – Revised November 2019
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Figure 5-2. Shared RAM (Dedicated to Subsystem)
Cortex-M3
Shared
RAM
(C2..Cn)
uDMA
5-3). These RAMs can be accessed by both CPUs (C28x/M3) and their respective
Table 5-1).
Figure 5-3. Shared RAM (Shared between Subsystems)
Cortex-M3
uDMA
Table 5-1. Master access for Sx RAM
(assuming all other protections are disabled)
M3 Read M3 Write uDMA
Read
Yes Yes Yes
Yes No Yes
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Shared
RAM
(L2..Ln)
C28x
Shared
RAM
(Sx
Memory)
DMA
uDMA C28x C28x
Write Fetch Read
Yes No Yes
No Yes Yes
RAM Control Module
C28x
DMA
C28x DMA DMA
Write Read Write
No Yes
Yes Yes
Internal Memory
No
Yes
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