I2C Slave Interrupt Clear (I2Csicr), Offset 0X818; I2C Slave Interrupt Clear (I2Csicr) Register; I2C Slave Masked Interrupt Status (I2Csmis) Register Field Descriptions; I2C Slave Interrupt Clear (I2Csicr) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 22-20. I2C Slave Masked Interrupt Status (I2CSMIS) Register Field Descriptions
Bit Field
31-3 Reserved
2 STOPMIS
1 STARTMIS
0 DATAMIS

22.7.7 I2C Slave Interrupt Clear (I2CSICR), offset 0x818

The I2C Slave Interrupt Clear (I2CSICR) register clears the raw interrupt. A read of this register returns no
meaningful data. It is shown in the table and figure below.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-21. I2C Slave Interrupt Clear (I2CSICR) Register Field Descriptions
Bit Field
31-3 Reserved
2 STOPIC
1 STARTIC
0 DATAIC
SPRUH22I – April 2012 – Revised November 2019
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Value Description
Reserved
Stop Condition Masked Interrupt Status. This bit is cleared by writing a 1 to the STOPIC bit in the
I2CSICR register
0 An interrupt has not occurred or is masked.
1 An unmasked STOP condition interrupt was signaled is pending.
Start Condition Masked Interrupt Status. This bit is cleared by writing a 1 to the STARTIC bit in the
I2CSICR register.
0 An interrupt has not occurred or is masked.
1 An unmasked START condition interrupt was signaled is pending
Data Masked Interrupt Status. This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register
0 An interrupt has not occurred or is masked.
1 An unmasked data received or data requested interrupt was signaled is pending.
Figure 22-31. I2C Slave Interrupt Clear (I2CSICR) Register
Reserved
R-0
Value Description
Reserved
Stop Condition Interrupt Clear.
0 Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register and the STOPMIS bit in the
I2CSMIS register. A read of this register returns no meaningful data.
0h Start Condition Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register and the STOPMIS bit in the
I2CSMIS register. A read of this register returns no meaningful data.
0h Data Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register and the STOPMIS bit in the
I2CSMIS register. A read of this register returns no meaningful data.
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Register Descriptions (I2C Slave)
3 2 1
STOPIC STARTIC
W-0 W-0
M3 Inter-Integrated Circuit (I2C) Interface
0
DATAIC
W-0
1511