Source Burst Step Size Register (Src_Burst_Step); Source Burst Step Size Register (Src_Burst_Step) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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11.8.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected
The source burst step size register (SRC_BURST_STEP) is shown in
Table 11-12.
Figure 11-17. Source Burst Step Size Register (SRC_BURST_STEP)
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-12. Source Burst Step Size Register (SRC_BURST_STEP) Field Descriptions
Bit Field
15-0 SRCBURSTSTEP
SPRUH22I – April 2012 – Revised November 2019
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SRCBURSTSTEP
R/W-0
Value Description
These bits specify the source address post-increment/decrement step size while
processing a burst of data:
0x0FFF Add 4095 to address
... ...
0x0002 Add 2 to address
0x0001 Add 1 to address
0x0000 No address change
0xFFFF Sub 1 from address
0xFFFE Sub 2 from address
... ...
0xF000 Sub 4096 from address
Only values from -4096 to 4095 are valid.
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Register Descriptions
Figure 11-17 and described in
C28 Direct Memory Access (DMA) Module
0
937