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19.6.9 Ethernet MAC Management Control (MACMCTL) Register, offset 0x020
The Ethernet MAC Management Control (MACMCTL) register enables software to control the transfer of
data to and from the MII Management registers in an external Ethernet PHY. The address, name, type,
reset configuration, and functional description of each of these registers can be found in
In order to initiate a read transaction from the MII Management registers, the WRITE bit must be cleared
during the same cycle that the START bit is set. In order to initiate a write transaction to the MII
Management registers, the WRITE bit must be set during the same cycle that the START bit is set.
Figure 19-13. Ethernet MAC Management Control (MACMCTL) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-12. Ethernet MAC Management Control (MACMCTL) Register Field Descriptions
Bit
Field
31-8
Reserved
7-3
REGADR
2
Reserved
1
WRITE
0
START
SPRUH22I – April 2012 – Revised November 2019
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Reserved
R-0
Value
Description
Reserved
MII Register Address
0h
The REGADR bit field represents the MII Management register address for the next MII
management interface transaction. Refer to
address that is not valid in the register map should not be written to, and any data read should be
ignored.
Reserved
MII Register Transaction Type
0
The next operation of the next MII management interface is a read transaction
1
The next operation of the next MII management interface is a write transaction
MII Register Transaction Enable
0
No effect.
1
The MII register located at REGADR is read (WRITE=0) or written (WRITE=1).
Copyright © 2012–2019, Texas Instruments Incorporated
Ethernet MAC Register Descriptions
8
7
3
2
REGADR
Reserved
R/W-0
R-0
Table 19-2
for the PHY register offsets. Note that any
M3 Ethernet Media Access Controller (EMAC)
Section
19.7.
1
0
WRITE
START
R/W-0
R/W-0
1397
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