Loopback Operation; Dma Operation; M3 Uart4 To C28 Sci-A Internal Loopback - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Functional Description
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a 1 to the
corresponding bit in the UART Interrupt Clear (UARTICR) register.
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is
received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes
empty through reading all the data (or by reading the holding register), or when a 1 is written to the
corresponding bit in the UARTICR register.

21.3.9 Loopback Operation

The UART can be placed into an internal loopback mode for diagnostic or debug work by setting the LBE
bit in the UARTCTL register. In loopback mode, data transmitted on the UnTx output is received on the
UnRx input.

21.3.10 DMA Operation

The UART provides an interface to the µDMA controller with separate channels for transmit and receive.
The DMA operation of the UART is enabled through the UART DMA Control (UARTDMACTL) register.
When DMA operation is enabled, the UART asserts a DMA request on the receive or transmit channel
when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted
whenever any data is in the receive FIFO. A burst transfer request is asserted whenever the amount of
data in the receive FIFO is at or above the FIFO trigger level configured in the UARTIFLS register. For the
transmit channel, a single transfer request is asserted whenever there is at least one empty location in the
transmit FIFO. The burst request is asserted whenever the transmit FIFO contains fewer characters than
the FIFO trigger level. The single and burst DMA transfer requests are handled automatically by the
μDMA controller depending on how the DMA channel is configured.
To enable DMA operation for the receive channel, set the RXDMAE bit of the DMA Control
(UARTDMACTL) register. To enable DMA operation for the transmit channel, set the TXDMAE bit of the
UARTDMACTL register. The UART can also be configured to stop using DMA for the receive channel if a
receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive error occurs,
the DMA receive requests are automatically disabled. This error condition can be cleared by clearing the
appropriate UART error interrupt.
If DMA is enabled, then the µDMA controller triggers an interrupt when a transfer is complete. The
interrupt occurs on the UART interrupt vector. Therefore, if interrupts are used for UART operation and
DMA is enabled, the UART interrupt handler must be designed to handle the µDMA completion interrupt.
See the Micro Direct Memory Access (µDMA) chapter for more details about programming the µDMA
controller.

21.4 M3 UART4 to C28 SCI-A Internal Loopback

The M3 UART4 peripheral can be internally connected to the C28 SCI-A peripheral. External GPIO pins
are not used when the loopback feature is enabled and can be used for other functions.
Figure 21-6 illustrates the loopback connections between the M3 UART4 and C28 SCI-A. The M3
UART4Rx is connected to C28 SCI-ATx and the M3 UART4Tx is connected to C28 SCI-ARx when
loopback is enabled. Loopback is enabled by setting the UART4TOSCIA bit in the M3 SERPLOOP
register. For a complete description of the SERPLOOP register, refer to the System Control and Interrupt
chapter.
1458
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
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SPRUH22I – April 2012 – Revised November 2019
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