Cpu Level Interrupt Handling - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Wait for any
PIEIFRx.y=1
Wait for
PIEIERx.y=1
Wait for
S/W to clear
PIEACKx bit=0
Interrupts
to CPU
NOTE: For multiplexed interrupts, the PIE responds with the highest priority interrupt that is both
flagged and enabled. If there is no interrupt both flagged and enabled, then the highest
priority interrupt within the group (INTx.1 where x is the PIE group) is used.
As shown in Table
the interrupt handling process being used. In the standard process, which happens most of the time, the
DBGIER register is not used. When the 28x is in real-time emulation mode and the CPU is halted, a
different process is used. In this special case, the DBGIER is used and the INTM bit is ignored. If the DSP
is in real-time mode and the CPU is running, the standard interrupt-handling process applies.
SPRUH22I – April 2012 – Revised November 2019
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Figure 1-5. CPU Level Interrupt Handling
Start
Stage A
No
PIEIFRx.y=1
?
Yes
Stage B
No
PIEIERx.y=1
?
Yes
Stage C
No
PIEACKx=0
?
Yes
Hardware sets
PIEACKx=1
Stage D
Interrupt request
sent to 28x CPU
on INTx
PIE interrupt control
1-9, the requirements for enabling the maskable interrupt at the CPU level depends on
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Exceptions and Interrupts Control
Stage E
IFRx bit set 1
Stage F
No
IERx bit=1
?
Yes
Stage G
No
INTM bit=0
?
Yes
Stage H
CPU responds
IFRx=0, IERx=0
INTM=1, EALLOW=0
Context Save performed
Stage I
Vector fetched from the PIE
PIEIFRx.y is cleared
CPU branches to ISR
Stage J
Interrupt service routine responds
Write 1 to PIEACKx bit to clear
to enable other interrupts in
PIEIFRx group
Re-enable interrupts, INTM=0
Return
End
CPU interrupt control
System Control and Interrupts
103