Fault Mask Register (Faultmask); Base Priority Mask Register (Basepri); Fault Mask Register (Faultmask) Field Descriptions; Base Priority Mask Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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24.4.4.7 Fault Mask Register (FAULTMASK)

The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is
only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK
register, and the CPS instruction may be used to change the value of the FAULTMASK register. See the
Cortex-M3 Instruction Set Technical User's Manualfor more information on these instructions. For more
information on exception priority levels, see .
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24-10. Fault Mask Register (FAULTMASK) Field Descriptions
Bit Field
31-1 Reserved
0 FAULTMASK

24.4.4.8 Base Priority Mask Register (BASEPRI)

The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a
nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the
BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This
register is only accessible in privileged mode. For more information on exception priority levels, see
Section 24.7.2.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-1 Reserved
7-5 BASEPRI
4-0 Reserved
SPRUH22I – April 2012 – Revised November 2019
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Figure 24-9. Fault Mask Register (FAULTMASK)
Reserved
R-0
Value Description
Reserved
Priority mask
0 No effect
1 Prevents the activation of all exceptions except for NMI.
Figure 24-10. Base Priority Mask Register (BASEPRI)
Reserved
R-0
Table 24-11. Base Priority Mask Register Field Descriptions
Value Description
Reserved
Base priority
Any exception that has a programmable priority level with the same or lower priority as the value of
this field is masked. The PRIMASK register can be used to mask all exceptions with programmable
priority levels. Higher priority exceptions have lower priority levels.
0h All exceptions are unmasked.
1h All exceptions with priority level 1-7 are masked
2h All exceptions with priority level 2-7 are masked
3h All exceptions with priority level 3-7 are masked.
4h All exceptions with priority level 4-7 are masked.
5h All exceptions with priority level 5-7 are masked.
6h All exceptions with priority level 6-7 are masked
7h All exceptions with priority level 7 are masked.
Software should not rely on the value of a reserved bit. To provide compatibility with future
products, the value of a reserved bit should be preserved across a read-modify-write operation.
Copyright © 2012–2019, Texas Instruments Incorporated
Programming Model
1
FAULTMASK
R/W-0
8 7 5 4
BASEPRI Reserved
R/W-0 R-0
Cortex-M3 Processor
0
0
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