Table of Contents
Advertisement
C-Boot ROM Description
6.6.4 C-Boot ROM Boot Modes
Unlike the master subsystem, the control subsystem doesn't support automatic detection of boot modes
using boot mode GPIO, because on Concerto it is up to the master subsystem application on how it wants
to boot the control subsystem. C-Boot ROM supports boot using IPC commands. The master subsystem
application can send certain IPC commands to C-Boot ROM to let the control subsystem boot.
shows different boot options supported by C-Boot ROM. These boot options programmed into the
MTOCIPCBOOTMODE register should be used in conjunction with the
"IPC_MTOC_EXECUTE_BOOTMODE_CMD" (value = 0x00000013) command in the MTOCIPCCOM
register as detailed in the next section.
C-Boot ROM Boot Mode
BOOT_FROM_RAM
BOOT_FROM_FLASH
BOOT_FROM_SCI
BOOT_FROM_SPI
BOOT_FROM_I2C
BOOT_FROM_PARALLEL
The master subsystem application must follow the below procedure to let the control subsystem boot as
commanded by master.
6.6.4.1
Master Application Procedure to Send Boot Mode IPC Commands to C-Boot ROM
The set of MTOCIPC registers mentioned in IPC section of the System Control and Interrupts chapter are
used to communicate and give commands to C-Boot ROM. The list of IPC commands supported by C-
Boot ROM is given in
master subsystem application to boot the control subsystem.
1. Check if C-Boot ROM is ready to accept IPC commands. If yes, then proceed to step 2 below, else,
wait. CTOMIPCBOOTSTS register is used by C-Boot ROM to communicate boot status to the master
subsystem. This will be explained in more detail in below sections of the document.
2. Configure the control subsystem C28x CPU as the owner for respective GPIO based on boot mode
using core select feature on the GPIO. In other words assign the required GPIO for boot to the C28x
core. Refer to
Table 6-20
3. MTOCIPCOM = MASTER_IPC_MTOC_EXECUTE_BOOTMODE_CMD
4. MTOCIPCBOOTMODE = C-Boot ROM Boot Mode command (as mentioned in
5. MTOCIPCSET = 0x80000001 (set bits 31 and 0 to enable respective bits in MTOCIPCFLG register)
MASTER_IPC_MTOC_EXECUTE_BOOTMODE_CMD mentioned in step 3 above is one of the IPC
commands supported by C-Boot ROM. The entire set of IPC commands supported by C-Boot ROM and
the detailed flow of on how the master subsystem can send an IPC command and how C-Boot ROM
handles the IPC commands is explained in detail in the subsequent sections of this chapter.
Refer to
Section 6.7
578
ROM Code and Peripheral Booting
Table 6-18. C-Boot ROM Boot Modes
MTOCIPCBOOTMODE Register Value
Section
6.6.9.3. This section explains how these IPC registers should be used by a
for more details on GPIO for each boot mode.
for more details on this procedure.
Copyright © 2012–2019, Texas Instruments Incorporated
0x00000001
On receiving this command from Master
subsystem, C-Boot ROM will branch to the
control subsystem RAM entry point
location and starts executing code from
there.
0x00000002
On receiving this command, C-Boot ROM
will branch to the control subsystem
FLASH entry point and starts executing
code from there.
0x00000003
On receiving this command C-Boot ROM
boots from the control subsystem SCI
peripheral.
0x00000004
On receiving this command C-Boot ROM
boots from the control subsystem SPI
interface.
0x00000005
On receiving this command, C-Boot ROM
boots from the control subsystem I2C
interface
0x00000006
On receiving this command, C-Boot ROM
boots from the control subsystem GPIO
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Table 6-18
Description
Table
6-18)
Submit Documentation Feedback
Advertisement
Chapters
Table of Contents
