System Control (Sysctrl) Register; System Control (Sysctrl) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

System Control Block (SCB) Register Descriptions
25.6.6 System Control (SYSCTRL) Register, offset 0xD10
The System Control (SYSCTRL) register controls features of entry to and exit from low-power state.
Note: This register can only be accessed from privileged mode.
31
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-44. System Control (SYSCTRL) Register Field Descriptions
Bit Field
31-5 Reserved
4 SEVONPEND
3 Reserved
2 SLEEPDEEP
1 SLEEPEXIT
0 Reserved
1636
Cortex-M3 Peripherals
Figure 25-37. System Control (SYSCTRL) Register
5 4
SEVONPEND
R/W-0
Value Description
Reserved
Wake Up on Pending
When an event or interrupt enters the pending state, the event signal wakes up the processor from
WFE. If the processor is not waiting for an event, the event is registered and affects the next
WFE.The processor also wakes up on execution of a SEV instruction or an external event.
0 Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded.
1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor.
Reserved
Deep Sleep Enable
0 Use Sleep mode as the low power mode.
1 Use Deep-sleep mode as the low power mode.
Sleep on ISR Exit
0 When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode.
1 When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an
ISR.
Setting this bit enables an interrupt-driven application to avoid returning to an empty main
application
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
Reserved SLEEPDEEP
R-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
16
1 0
SLEEPEXIT Reserved
R/W-0 R-0
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