Flash Bank Pump Control Register (Fbprdy); Flash Bank Pump Control Register 1 (Fpac1); Flash Bank Pump Control Register (Fbprdy) Field Descriptions; Flash Bank Pump Control Register 1 (Fpac1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Flash Registers
5.4.1.5 Flash Bank Pump Control Register 1 (FBPRDY)
31
15 14
PUMPRDY
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-90. Flash Bank Pump Control Register (FBPRDY) Field Descriptions
Bit Field
31-16 Reserved
15 PUMPRDY
14-1 Reserved
0 BANKRDY
5.4.1.6

Flash Bank Pump Control Register 1 (FPAC1)

31
Reserved
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-91. Flash Bank Pump Control Register 1 (FPAC1) Field Descriptions
Bit Field
31-27 Reserved
26-16 PSLEEP
15-1 Reserved
514
Internal Memory
Figure 5-86. Flash Bank Pump Control Register (FBPRDY)
Value Description
Reserved
Pump Ready. This is a read-only bit which allows software to determine if the pump is ready for
flash access before attempting the actual access. If an access is made to a bank when the pump is
not ready, wait states are asserted until it becomes ready.
0 Pump is not ready.
1 Pump is ready, in active power state.
Reserved
Bank Ready. This is a read-only register which allows software to determine if the M3 bank is ready
for Flash access before the access is attempted.
Note: The user should wait for both the pump and the bank to be ready before attempting an
access.
0 M3 bank is not ready.
1 M3 bank is in active power mode and is ready for access.
Figure 5-87. Flash Bank Pump Control Register 1 (FPAC1)
R-0
Reserved
R-0
Value Description
Reserved
Pump sleep. These bits contain the starting count value for the charge pump sleep down counter.
While the charge pump is in sleep mode, the power mode management logic holds the charge
pump sleep counter at this value. When the charge pump exits sleep power mode, the down
counter delays from 0 to PSLEEP prescaled M3 SYSCLK clock cycles before putting the charge
pump into active power mode.
Note: The pump sleep down counter uses the same prescaled clock as Bank sleep down counter
which is divided by 2 of input M3 SYSCLK. For a clock operating at 150 Mhz, the following is the
formula used in the obtaining the correct psleep:
PSLEEP = PSLEEP_REQ_ns / 2 / HCLK_period_ns
PSLEEP = 20000/2/6.66 (in decimal)
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
Reserved
R-0
27 26
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
1 0
BANKRDY
R-0
16
PSLEEP
R/W-0x64
1 0
PMPPWR
R/W-0
Submit Documentation Feedback
16