Data High Test Register (Fdatah_Test); Data Low Test Register (Fdatal_Test); Ecc Test Address Register (Faddr_Test); Ecc Test Register (Fecc_Test) - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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5.4.4.11 Data High Test Register (FDATAH_TEST)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-133. Data High Test Register (FDATAH_TEST) Field Descriptions
Bit Field
31-0 FDATAH

5.4.4.12 Data Low Test Register (FDATAL_TEST)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-134. Data Low Test Register (FDATAL_TEST) Field Descriptions
Bit Field
31-0 FDATAL

5.4.4.13 ECC Test Address Register (FADDR_TEST)

31
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-135. ECC Test Address Register (FADDR_TEST) Field Descriptions
Bit Field
31-19 Reserved
18-0 ADDR

5.4.4.14 ECC Test Register (FECC_TEST)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Figure 5-129. Data High Test Register (FDATAH_TEST)
Value Description
High double word of selected 64-bit data. User-configurable bits 63:32 of the selected data blocks
in ECC test mode.
Figure 5-130. Data Low Test Register (FDATAL_TEST)
Value Description
Low double word of selected 64-bit data. User-configurable bits 31:0 of the selected data blocks in
ECC test mode.
Figure 5-131. ECC Test Address Register (FADDR_TEST)
19 18
Value Description
Reserved
Address for selected 64-bit data. User-configurable address bits of the selected data in
ECC test mode.
Figure 5-132. ECC Test Register (FECC_TEST)
Reserved
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
FDATAH
R/W-0
FDATAL
R/W-0
ADDR
R/W-0
Flash Registers
8 7
ECC
R/W-0
Internal Memory
0
0
0
0
533