Chip Select Configuration Register Assignment; Capabilities Of Host Bus 8 And Host Bus 16 Modes - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Host Bus Mode
Configuration Register
EPIHBnCFG
EPIHBnCFG2
EPIHBnCFG3
EPIHBnCFG4
(1)
If the CSBAUD bit in the EPIHBnCFG2 register is clear and multiple chip selects are enabled, then all chip selects are
configured by the MODE bit field in the EPIHBnCFG register.
Note that multiple chip select modes do not allow the intermixing of Host-Bus 8 and Host-Bus16 modes.
When BSEL=1 in the EPIHB16CFG register, byte select signals are provided, so byte-sized data can be
read and written at any address; however, these signals reduce the available address width by two pins.
The byte select signals are active Low. BSEL0 corresponds to the LSB of the halfword, and BSEL1
corresponds to the MSB of the halfword.
When BSEL=0, byte reads and writes at odd addresses only act on the even byte, and byte writes at even
addresses write invalid values into the odd byte. As a result, accesses should be made as half-words (16-
bits) or words (32-bits). In C/C++, programmers should use only short int and long int for accesses. Also,
because data accesses in HB16 mode with no byte selects are on 2-byte boundaries, the available
address space is doubled. For example, 28 bits of address accesses 512 MB in this mode.
shows the capabilities of the HB8 and HB16 modes as well as the available address bits with the possible
combinations of these bits.
Although the EPI0S31 signal can be configured for the EPI clock signal in Host-Bus mode, it is not
required and should be configured as a GPIO to reduce EMI in the system.
Host Bus Mode
Type
HB8 0x0
HB8 0x0
HB8 0x0
HB8 0x0
HB8 0x0
HB8 0x0
HB8 0x1
HB8 0x1
HB8 0x1
HB8 0x1
HB8 0x1
HB8 0x1
HB8 0x3
HB16 0x0
HB16 0x0
HB16 0x0
HB16 0x0
HB16 0x0
HB16 0x0
HB16 0x0
HB16 0x0
HB16 0x0
(1)
If byte selects are not used, data accesses are on 2-byte boundaries. As a result, the available address space is doubled.
(2)
Two EPI signals are used for byte selects, reducing the available address space by two bits.
1202
External Peripheral Interface (EPI)
Table 17-4. Chip Select Configuration Register Assignment
(1)
Table 17-5. Capabilities of Host Bus 8 and Host Bus 16 Modes
CSCFGEXT CSCFG
0 0x0,0x1
0 0x2
0 0x3
1 0x0
1 0x1
1 0x2
0 0x0,0x1
0 0x2
0 0x3
1 0x0
1 0x1
1 0x2
X X
0 0x0,0x1
0 0x0,0x1
0 0x2
0 0x2
0 0x3
0 0x3
1 0x0
1 0x0
1 0x1
Copyright © 2012–2019, Texas Instruments Incorporated
Corresponding Chip Select
CS0
CS1
CS2
CS3
Max # of BSEL Byte
External Access
Devices
1 N/A Always
2 N/A Always
2 N/A Always
1 N/A Always
4 N/A Always
4 N/A Always
1 N/A Always
2 N/A Always
2 N/A Always
1 N/A Always
4 N/A Always
4 N/A Always
- N/A Always
1 0
1 1
2 0
2 1
2 0
2 1
1 0
1 1
4 0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Table 17-5
Available Addressabl
Address e Memory
28 256 MB
27 128 MB
26 64 MB
27 128 MB
27 128 MB
26 64 MB
20 1 MB
19 512 KB
18 256 KB
19 512 MB
19 512 MB
18 256 MB
None
(1)
No 28 512 MB
(2)
Yes 26 64 MB
(1)
No 27 256 MB
(2)
Yes 25 32 MB
(1)
No 26 128 MB
(2)
Yes 24 16 MB
(1)
No 27 256 MB
(2)
Yes 25 32 MB
(1)
No 27 256 MB
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