Register Map; Universal Serial Bus (Usb) Controller Register Map - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Map

Configuring each endpoint's FIFO involves reserving a portion of the overall USB FIFO RAM to each
endpoint. The total FIFO RAM available is 4 Kbytes with the first 64 bytes reserved for endpoint 0. The
endpoint's FIFO must be at least as large as the maximum packet size. The FIFO can also be configured
as a double-buffered FIFO so that interrupts occur at the end of each packet and allow filling the other half
of the FIFO.
If operating as a device, the USB device controller's soft connect must be enabled when the device is
ready to start communications, indicating to the host controller that the device is ready to start the
enumeration process. If operating as a Host controller, the device soft connect must be disabled and
power must be provided to VBUS via the USB0EPEN signal.
18.4 Register Map
Table 18-4 lists the registers. All addresses given are relative to the USB base address of 0x4005.0000.
Note that the USB controller clock must be enabled before the registers can be programmed (see the
System Control chapter).
Table 18-4. Universal Serial Bus (USB) Controller Register Map
Offset Name
(1)
0x000 USBFADDR
(1)(2)
0x001 USBPOWER
(1)(2)
0x002 USBTXIS
(1)(2)
0x004 USBRXIS
(1)(2)
0x006 USBTXIE
(1)(2)
0x008 USBRXIE
(1)(2)
0x00A USBIS
(1)(2)
0x00B USBIE
(1)(2)
0x00C USBFRAME
(1)(2)
0x00E USBEPIDX
(1)(2)
0x00F USBTEST
(1)(2)
0x020 USBFIFO0
(1)(2)
0x024 USBFIFO1
(1)(2)
0x028 USBFIFO2
(1)(2)
0x02C USBFIFO3
(1)(2)
0x030 USBFIFO4
(1)(2)
0x034 USBFIFO5
(1)(2)
0x038 USBFIFO6
(1)(2)
0x03C USBFIFO7
(1)(2)
0x040 USBFIFO8
(1)(2)
0x044 USBFIFO9
(1)(2)
0x048 USBFIFO10
(1)(2)
0x04C USBFIFO11
(1)(2)
0x050 USBFIFO12
(1)(2)
0x054 USBFIFO13
(1)(2)
0x058 USBFIFO14
(1)(2)
0x05C USBFIFO15
(2)
0x060 USBDEVCTL
(1)(2)
0x062 USBTXFIFOSZ
(1)(2)
0x063 USBRXFIFOSZ
(1)(2)
0x064 USBTXFIFOADD
(1)(2)
0x066 USBRXFIFOADD
(1)(2)
0x07A USBCONTIM
(3)
0x07B USBVPLEN
1292
M3 Universal Serial Bus (USB) Controller
Type Reset Description
R/W 0x00 USB Device Functional Address
R/W 0x20 USB Power
RO 0x0000 USB Transmit Interrupt Status
RO 0x0000 USB Receive Interrupt Status
R/W 0xFFFF USB Transmit Interrupt Enable
R/W 0xFFFE USB Receive Interrupt Enable
RO 0x00 USB General Interrupt Status
R/W 0x06 USB Interrupt Enable
RO 0x0000 USB Frame Value
R/W 0x00 USB Endpoint Index
R/W 0x00 USB Test Mode
R/W 0x0000.0000 USB FIFO Endpoint 0
R/W 0x0000.0000 USB FIFO Endpoint 1
R/W 0x0000.0000 USB FIFO Endpoint 2
R/W 0x0000.0000 USB FIFO Endpoint 3
R/W 0x0000.0000 USB FIFO Endpoint 4
R/W 0x0000.0000 USB FIFO Endpoint 5
R/W 0x0000.0000 USB FIFO Endpoint 6
R/W 0x0000.0000 USB FIFO Endpoint 7
R/W 0x0000.0000 USB FIFO Endpoint 8
R/W 0x0000.0000 USB FIFO Endpoint 9
R/W 0x0000.0000 USB FIFO Endpoint 10
R/W 0x0000.0000 USB FIFO Endpoint 11
R/W 0x0000.0000 USB FIFO Endpoint 12
R/W 0x0000.0000 USB FIFO Endpoint 13
R/W 0x0000.0000 USB FIFO Endpoint 14
R/W 0x0000.0000 USB FIFO Endpoint 15
R/W 0x80 USB Device Control 53
R/W 0x00 USB Transmit Dynamic FIFO Sizing
R/W 0x00 USB Receive Dynamic FIFO Sizing
R/W 0x0000 USB Transmit FIFO Start Address
R/W 0x0000 USB Receive FIFO Start Address
R/W 0x5C USB Connect Timing
R/W 0x3C USB OTG VBUS Pulse Timing
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SPRUH22I – April 2012 – Revised November 2019
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Section
Section 18.5.1
Section 18.5.2
Section 18.5.3
Section 18.5.4
Section 18.5.5
Section 18.5.6
Section 18.5.7
Section 18.5.8
Section 18.5.9
Section 18.5.10
Section 18.5.11
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.12
Section 18.5.13
Section 18.5.14
Section 18.5.15
Section 18.5.16
Section 18.5.17
Section 18.5.18
Section 18.5.19