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Multiple Clock Source
23.3 Multiple Clock Source
Three clock domains are provided to the CAN module for generating the CAN bit timing: the external
oscillator clock (X1/X2), the M3 system clock, and the GPIO XCLKIN.
The system module reference guide and the device data manual provide for more information on how to
configure the relevant clock source registers in the system module.
NOTE: The CAN core has to be programmed to at least eight clock cycles per bit time. To achieve a
transfer rate of 1 Mbps an oscillator frequency of 8 MHz or higher has to be used.
23.4 Interrupt Functionality
Interrupts can be generated on two interrupt lines: CAN0INT and CAN1INT. These lines can be enabled
by setting IE0 and IE1 bits, respectively, in the CAN Control register.
The CAN provides three groups of interrupt sources: message object interrupts, status change interrupts
and error interrupts. The source of an interrupt can be determined by the interrupt identifiers INT0ID and
INT1ID in the CAN_INT Interrupt register (see
will hold the value zero. Each interrupt line remains active until the dedicated field in the Interrupt register
(INT0ID or INT1ID) again reaches zero (this means the cause of the interrupt is reset), or until IE0 or IE1
are reset. The value 0x8000 in the INT0ID field indicates that an interrupt is pending because the CAN
core has updated (not necessarily changed) the Error and Status register (Error Interrupt or Status
Interrupt). This interrupt has the highest priority. The CPU can update (reset) the status bits WakeUpPnd,
RxOk, TxOk and LEC by reading the Error and Status register, but a write access of the CPU will never
generate or reset an interrupt.
Values between 1 and the number of the last message object indicates that the source of the interrupt is
one of the message objects. INT0ID or INT1ID will point to the pending message interrupt with the highest
priority. Message Object 1 has the highest priority and the last message object has the lowest priority.
An interrupt service routine which reads the message that is the source of the interrupt, may read the
message and reset the message object's IntPnd at the same time (ClrIntPnd bit in the IF1 and IF2
Command register). When IntPnd is cleared, the Interrupt register will point to the next message object
with a pending interrupt.
23.4.1 Message Object Interrupts
Message object interrupts are generated by events from the message objects. They are controlled by the
flags IntPND, TxIE and RxIE which are described in
routed to either CAN0INT or CAN1INT line, controlled by the Interrupt Multiplexer register, see
Section
23.15.13. Note that writing to the IntPnd bit in the CAN_IFnMCTL registers can force an interrupt.
23.4.2 Status Change Interrupts
The events WakeUpPnd, RxOk, TxOk and LEC in Error and Status register (see
to the status change interrupts. The status change interrupt group can be enabled by bit SIE in CAN
Control register (see
CAN frame, independent of bus errors or valid CAN communication, and also independent of the Message
RAM configuration. Status Change interrupts can only be routed to interrupt line CAN0INT which has to be
enabled by setting IE0 in the CAN Control register.
NOTE: Reading the Error and Status register will clear the WakeUpPnd flag. If in global power-down
mode, the WakeUpPnd flag is cleared by such a read access before the CAN module has
been woken up by the system, the CAN may reassert the WakeUpPnd flag, and a second
interrupt may occur. See also
1520
M3 Controller Area Network (CAN)
Section
23.15.1). If SIE is set, a status change interrupt will be generated at each
Section
23.5.2).
Copyright © 2012–2019, Texas Instruments Incorporated
Section
23.15.5). When no interrupt is pending, the register
Section
23.14.1. Message object interrupts can be
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Section
23.15.2) belong
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