Table of Contents
Advertisement
Register Descriptions
Table 21-9. UART Line Control Register (UARTLCRH) Field Descriptions (continued)
Bit
Field
3
STP2
2
EPS
1
PEN
0
BRK
21.7.8 UART Control Register (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit
Enable (TXE) and Receive Enable (RXE) bits, which are set.
To enable the UART module, the UARTEN bit must be set. If software requires a configuration change in
the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is
disabled during a transmit or receive operation, the current transaction is completed prior to the UART
stopping.
The UARTCTL register should not be changed while the UART is enabled or else the results are
unpredictable. The following sequence is recommended for making changes to the UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by clearing bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
31
7
6
LBE
LIN
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1468
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Value
Description
UART Two Stop Bits Select
0
One stop bit is transmitted at the end of a frame.
1
Two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop
bits being received. When in 7816 smartcard mode (the SMART bit is set in the UARTCTL
register), the number of stop bits is forced to 2.
UART Even Parity Select
This bit has no effect when parity is disabled by the PEN bit.
0
Odd parity is performed, which checks for an odd number of 1s.
1
Even parity generation and checking is performed during transmission and reception, which checks
for an even number of 1s in data and parity bits.
UART Parity Enable
0
Parity is disabled and no parity bit is added to the data frame.
1
Parity checking and generation is enabled.
UART Send Break
0
Normal use.
1
A Low level is continually output on the UnTx signal, after completing transmission of the current
character. For the proper execution of the break command, software must set this bit for at least
two frames (character periods).
Figure 21-15. UART Control (UARTCTL) Register
Reserved
R-0
5
4
HSE
EOT
R/W-0
R/W-0
Copyright © 2012–2019, Texas Instruments Incorporated
10
3
2
SMART
SIRLP
R/W-0
R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
9
8
RXE
TXE
R/W-1
R/W-1
1
0
SIREN
UARTEN
R/W-0
R/W-0
Submit Documentation Feedback
Advertisement
Chapters
Table of Contents
