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Flash Controller Memory Module
needs to be executed from RAM should be copied from Flash at run time.
•
Users must check and install available updates for CCS On-Chip Flash Plugin and UniFlash tools.
5.3.3 Default Flash Configuration
The following are flash module configuration settings at power-up, in both master and control subsystems:
•
Dedicated flash banks are in sleep power mode
•
Shared pump is in sleep mode
•
ECC is enabled
•
Wait-states are set to max (0xF)
•
Program cache and data cache are disabled in M3-FMC
•
Code-prefetch mechanism and data cache are disabled in C28x-FMC
Note that during the boot process, the boot ROM performs a dummy read of the Code Security Module
(CSM) password locations located in the flash. This read is performed to unlock a new (or erased) device
that has no password stored in it, so that flash programming or loading of code into CSM protected
SARAM can be performed. On devices with a password, this read has no effect and the device remains
locked. One effect of this read is that the flash will transition from the sleep (reset) state to the active state.
User application software must initialize wait-states using the FRDCNTL register, and configure
cache/prefetch features using the RD_INTF_CTRL register, to achieve optimum system performance.
Software that configures flash settings like wait-states, cache/prefetch features, and so on, must be
executed only from RAM memory, not from flash memory.
NOTE: Before initializing wait-states, cache/prefetch mechanisms must always be disabled, if they
are enabled. After the initialization of wait-states is done, cache/prefetch mechanisms can be
enabled as needed.
5.3.4 Flash Bank, OTP and Pump
There is a dedicated flash bank in the master subsystem called the M3 flash bank and a dedicated flash
bank in the control subsystem called the C28x flash bank. Also, there is a one-time programmable (OTP)
memory on the master subsystem called USER OTP which the user can program only once and cannot
erase. Flash and OTP are uniformly mapped in both program and data memory space.
Both the master subsystem and control subsystem have a TI-OTP which contains manufacturing
information like settings used by the flash state machine for erase and program operations, and so on.
Users may read TI-OTP but cannot program or erase. For memory map and size information of the M3
flash bank, M3 TI-OTP, M3 User OTP, C28x flash bank, C28x TI-OTP and corresponding ECC locations,
please refer to the device data manual.
The M3 flash bank/User OTP and C28x flash bank share a common flash pump. A hardware semaphore,
called the flash pump semaphore, is provided to control the access of the flash pump between the master
subsystem and control subsystem. Refer to the System Control and Interrupts chapter for more
information on usage of flash pump semaphore
Table 5-83
provides the user-programmable OTP locations in M3 OTP. For more information on the
functionality of these fields, please refer to the System Control and Interrupts chapter and the ROM Code
and Peripheral Booting chapter.
Name
OTPSECLOCK
Z2_FLASH_ENTRY_POINT
494
Internal Memory
Table 5-83. Programmable OTP Locations in M3 OTP
Address
0x680800
0x68080C
Copyright © 2012–2019, Texas Instruments Incorporated
Size (x8)
Description
4
Contents of this OTP location gets copied to
the OTPSECLOCK register
4
Alternate flash entry point can be programmed
in this OTP location
SPRUH22I – April 2012 – Revised November 2019
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