Clock Sources; Plls - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Clock Control

1.8.1 Clock Sources

There are four possible reference clock sources in this device:
• OSCCLK (from X1 or X1/X2 pins)
• GPIO_XCLKIN is a single ended clock input
• Internal 10 MHz OSCCLK (INTOSC)
• Internal 32 kHz clock derived from the internal 10 MHz oscillator
OSCCLK is always used as the reference clock source to generate the system clock. OSCCLK or
GPIO_XCLKIN can be used to generate the 60 MHz USB clock. The INTOSC clock is used for missing
clock condition detection and also to generate a low frequency 32 kHz clock in low power deep sleep
modes. In deep sleep mode, the PLLs and X1/X2 are off.
The following sections give more details on each clock source.
1.8.1.1 OSCCLK
The oscillator provides a frequency-accurate clock source by one of two means: an external single-ended
clock source is connected to the X1 input pin, or an external crystal is connected across the X1 input and
X2 output pins. The crystal value must be one of the supported frequencies as mentioned in the device
data manual. When used as a clock input to the system PLL, the single-ended clock source should be in
the range mentioned in the device data manual. OSCCLK can also be a clock source for the USB PLL. A
resonator can also be used as an input clock source on the X1/X2 pins.
1.8.1.2 GPIO_XCLKIN
GPIO_XCLKIN is a clock input which is available when the PJ7_GPIO63 pin is used as a clock input. This
clock input can be used as a clock source only to the USB PLL and the CAN modules of the master
subsystem.
1.8.1.3 10 MHz INTOSC
The internal oscillator is a 10 MHz on-chip clock source, which is used as the clock source in the event
the main oscillator clock goes missing. It does not require the use of any external components and
provides a clock that is 10 MHz. This clock should not be used as a normal run mode clock as it is just a
clock for error handling in case the main OSCCLK goes missing. This clock can also be used as a clock
source for the deep-sleep mode of the device if configured by the DSLPCLKCFG register.
1.8.1.4 32-kHz Clock
The 32-kHz clock is derived from the internal oscillator by clock division from 10 MHz to 32 kHz. This
clock is intended for use during deep-sleep power-saving modes. This power-savings mode benefits from
reduced internal switching and also allows the OSCCLK to be powered down if configured by the
DSLPCLKCFG register.
The following limits apply to X1 and XCLKIN frequencies for DCAN0/1, WDT1, and USB peripherals:
• X1 can be clocked up to 100 MHz, if the clock input meets the expected duty cycle and jitter as
mentioned in the data manual.
• XCLKIN input pin frequency is limited to 60 MHz.
• If DCAN0 or DCAN1 is clocked from the X1 (OSCLK) source, then it cannot exceed 100 MHz.
• If DCAN0 or DCAN1 is clocked from the XCLKIN source, then it cannot exceed 60 MHz.
• If the USB is clocked from the XCLKIN source, then it cannot exceed 60 MHz.

1.8.2 PLLs

There are two PLLs in this device; one used to generate the clocks for the entire device (system PLL) and
the other to generate the fixed 60 MHz clock to the USB module (USB PLL). The clock input source to the
system PLL is OSCCLK and USBPLL is OSCCLK or GPIO_XCLKIN. Both the PLLs are powered down in
the deep sleep mode.
126
System Control and Interrupts
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SPRUH22I – April 2012 – Revised November 2019
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