Uart Interrupt Clear (Uarticr), Offset 0X044; Uart Interrupt Clear (Uarticr) Register; Uart Interrupt Clear (Uarticr) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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21.7.13 UART Interrupt Clear (UARTICR), offset 0x044

The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw
interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
31
23
15 14
LME5MIC LME1MIC
W/1C-0 W/1C-0
7 6
FEIC RTIC
W/1C-0 W/1C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-15. UART Interrupt Clear (UARTICR) Register Field Descriptions
Bit Field
31-16 Reserved
15 LME5MIC
14 LME1MIC
13 LMSBMIC
12-11 Reserved
10 OEIC
9 BEIC
8 PEIC
7 FEIC
6 RTIC
5 TXIC
4 RXIC
3-0 Reserved
SPRUH22I – April 2012 – Revised November 2019
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Figure 21-20. UART Interrupt Clear (UARTICR) Register
13 12
LMSBMIC
W/1C-0
5 4
TXIC RXIC
W/1C-0 W/1C-0
Value Description
Reserved
LIN Mode Edge 5 Interrupt Clear
Writing a 1 to this bit clears the LME5RIS bit in the UARTRIS register and the LME5MIS bit in the
UARTMIS register.
LIN Mode Edge 1 Interrupt Clear
Writing a 1 to this bit clears the LME1RIS bit in the UARTRIS register and the LME1MIS bit in the
UARTMIS register.
LIN Mode Sync Break Interrupt Clear
Writing a 1 to this bit clears the LMSBRIS bit in the UARTRIS register and the LMSBMIS bit in the
UARTMIS register.
Reserved
Overrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and the OEMIS bit in the
UARTMIS register.
Break Error Interrupt Clear
Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and the BEMIS bit in the
UARTMIS register.
Parity Error Interrupt Clear
Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and the PEMIS bit in the
UARTMIS register.
Framing Error Interrupt Clear
Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and the FEMIS bit in the
UARTMIS register.
Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and the RTMIS bit in the
UARTMIS register.
Transmit Interrupt Clear
Writing a 1 to this bit clears the TXRIS bit in the UARTRIS register and the TXMIS bit in the
UARTMIS register.
Receive Interrupt Clear
Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and the RXMIS bit in the
UARTMIS register.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
Reserved
R-0
11 10
Reserved OEIC
R-0 W/1C-0
3
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Register Descriptions
24
16
9 8
BEIC PEIC
W/1C-0 W/1C-0
0
Reserved
R-0
1477