Register Map; Gpio Interrupt Configuration Example - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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General-Purpose Input/Output (GPIO)

0=Low level,

X=Ignored (don't care bit)

4.1.5 Register Map

lists the GPIO registers. Each GPIO port can be accessed through one of two bus apertures.

The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible with existing software.

The other aperture, the Advanced High-Performance Bus (AHB), offers the same register map but

provides better back-to-back access performance than the APB bus.

NOTE: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending

on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to

unconnected bits has no effect, and reading unconnected bits returns no meaningful data.

The offset listed is a hexadecimal increment to the register's address, relative to that GPIO port's base

GPIO Port A (APB): 0x4000.4000

GPIO Port A (AHB): 0x4005.8000

GPIO Port B (APB): 0x4000.5000

GPIO Port B (AHB): 0x4005.9000

GPIO Port C (APB): 0x4000.6000

GPIO Port C (AHB): 0x4005.A000

GPIO Port D (APB): 0x4000.7000

GPIO Port D (AHB): 0x4005.B000

GPIO Port E (APB): 0x4002.4000

GPIO Port E (AHB): 0x4005.C000

GPIO Port F (APB): 0x4002.5000

GPIO Port F (AHB): 0x4005.D000

GPIO Port G (APB): 0x4002.6000

GPIO Port G (AHB): 0x4005.E000

GPIO Port H (APB): 0x4002.7000

GPIO Port H (AHB): 0x4005.F000

GPIO Port J (APB): 0x4003.D000

GPIO Port J (AHB): 0x4006.0000

GPIO Port K (AHB): 0x4006.1000

General-Purpose Input/Output (GPIO)

Table 4-4. GPIO Interrupt Configuration Example

Pin 2 Bit Value

SPRUH22I – April 2012 – Revised November 2019

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