Flash Cache Mode - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Flash Controller Memory Module
The program cache/prefetch mecahnism and data cache are bypassed in standard read mode; therefore,
every access to the flash/OTP is used by the CPU immediately and every access creates a unique flash
bank access.
Standard read mode is the recommended mode for lower system frequency operation in which RWAIT
can be set to zero to provide single cycle access operation. FMC can operate at higher frequencies using
standard read mode at the expense of adding wait states. At higher system frequencies, it is
recommended to enable cache and prefetch mechanisms to improve performance. Please refer to device
specific data manual to determine maximum flash frequency allowed in standard read mode (i.e.,
maximum flash clock frequency with one wait state - FCLKmax).
5.3.8.1.2 Cache Mode
5.3.8.1.2.1 Program Cache
Flash memory is typically used to store application code. During code execution, instructions are fetched
from sequential memory addresses, except when a discontinuity occurs. Usually, the portion of the code
that resides in sequential addresses makes up the majority of the application code, and is referred to as
linear code. To improve the performance of linear code execution, a flash prefetch-mechanism has been
implemented in FMC. This prefetch mechanism does a look-ahead prefetch on linear address increments
starting from the address of the last program access.
Apart from linear code, in general application codes, there may be several loops wherein a set of
instructions located in sequential addresses are executed repeatedly in a loop, until a condition holds true.
To improve the performance of small loop code execution, an 8-level deep 128-bit wide (8 x 128) direct
mapped program cache has been implemented in the FMC. Whenever instructions in cache are fetched
for CPU processing, the flash prefetch mechanism does a look-ahead prefetch of 128 bits from the next
linear 128-bit aligned address from last address access, and fills the program cache as shown in
79.

Flash cache mode

M
Cortex
U
M3
32-bit
X
CPU
498
Internal Memory
Figure 5-79. Flash Cache Mode
8 x 128-bit
Direct mapped
program cache
Instruction fetch
128-bit data cache
Copyright © 2012–2019, Texas Instruments Incorporated
Look ahead prefetch
128-bit prefetch data
Data from DCODE access
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Figure 5-
Flash and OTP
8-bit
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