Dma Block Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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SHARED
SHARED
RESOURCES
RESOURCES
ANALOG SUBSYSTEM
ANALOG SUBSYSTEM
ACIB
ACIB
ADC1
ADC1
RESULT
RESULT
REGISTES
REGISTERS
ADC2
ADC2
RESULT
RESULT
REGISTERS
REGISTES
11.2.2 Peripheral Interrupt Event Trigger Sources
The peripheral interrupt event trigger can be independently configured as one twenty-nine different
sources for each of the six DMA channels. Included in these sources are three external interrupt signals
which can be connected to most of the general-purpose input/output (GPIO) pins on the device. This adds
significant flexibility to the event trigger capabilities. A bit field called PERINTSEL in the MODE register of
each channel is used to select that channels interrupt trigger source. An active peripheral interrupt trigger
will be latched into the PERINTFLG bit of the CONTROL register, and if the respective interrupt and DMA
channel is enabled (see the MODE.CHx[PERINTE] and CONTROL.CHx[RUNSTS] bits), it will be serviced
by the DMA channel. Upon receipt of a peripheral interrupt event signal, the DMA will automatically send a
clear signal to the interrupt source so that subsequent interrupt events will occur.
Regardless of the value of the MODE.CHx[PERINTSEL] bit field, software can always force a trigger by
using the CONTROL.CHx[PERINTFRC] bit. Likewise, software can always clear a pending DMA trigger
using the CONTROL.CHx[PERINTCLR] bit.
SPRUH22I – April 2012 – Revised November 2019
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Figure 11-1. DMA Block Diagram
S0-S7
S0-S7
MTOC
MTOC
CTOM
CTOM
SHARED
SHARED
MSG
MSG
MSG
MSG
RAM
RAM
RAM
RAM
RAM
RAM
(parity)
(parity)
(parity)
(parity)
(parity)
(parity)
PF3
PF3
Copyright © 2012–2019, Texas Instruments Incorporated
C28x
C28x
L2/L3
L2/L3
LOCAL
LOCAL
RAM
RAM
MEMORY
MEMORY
(parity)
(parity)
C28 CPU BUS
C28 CPU BUS
PIE
PIE
DINTCH (6:1)
DINTCH (6:1)
MXINTA, MRINTA
MXINTA, MRINTA
ADCINT (4:1)
ADCINT (4:1)
C28x
C28x
SOCA (9:1), SOCB(9:1)
SOCA (9:1), SOCB(9:1)
DMA
DMA
XINT 1,2,3
XINT 1,2,3
TINT 0,1,2
TINT 0,1,2
C28 DMA BUS
C28 DMA BUS
C28x
C28x
PERIPHERALS
PERIPHERALS
C28 Direct Memory Access (DMA) Module
Architecture
C28x
C28x
CPU
CPU
913

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