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Flash Controller Memory Module
Address/Double-bit data error
Single-bit Error position
Address/Double-bit data error
Single-bit Error position
During an instruction fetch or data read operation, the 19 address bits (three least significant bits of
address are not considered), together with the 64-bit data/8-bit ECC read-out of flash banks/ECC memory
map area, pass through the SECDED logic and the eight check bits are produced in FMC. These eight
calculated ECC check bits are then XORed with the stored check bits (user-programmed check bits)
associated with the address and the read data. The 8-bit output is decoded inside the SECDED module to
determine one of three conditions:
•
No error occurred
•
A correctable error (single bit data error) occurred
•
A non-correctable error (double bit data error or address error) occurred
If the SECDED logic finds a single bit error in the address field, then it is considered to be a non-
correctable error.
NOTE: Since ECC is calculated for an entire 64-bit data, a non 64-bit read such as a byte read or a
half-word read will still force the entire 64-bit data to be read and calculated, but only the
byte or half-word will be actually used by the CPU.
This ECC (SECDED) feature is enabled at reset. The ECC_ENABLE register can be used to configure
(enable or disable) the ECC feature. The ECC for the application code must be programmed.
There are two SECDED modules in each FMC. Out of the 128-bit data (aligned on a 128-bit memory
boundary) read from the bank/OTP address, the lower 64-bits of data and corresponding 8 ECC bits (read
from user programmable ECC memory area) are fed as inputs to one SECDED module along with the
128-bit aligned 19-bit address from where data has been read. The upper 64-bits of data and
corresponding 8 ECC bits are fed as inputs to another SECDED module in parallel along with 128-bit
aligned 19-bit address. Each of the SECDED modules evaluate their inputs and determine if there is any
single bit data error or double bit data error/address error.
ECC logic will be bypassed when the 64 data bits and the associated ECC bits fetched from the bank are
either all ones or zeros.
504
Internal Memory
Figure 5-81. ECC Logic Inputs and Outputs
Single-bit data error
Corrected data out
128-bit aligned 19-bit CPU address
Single-bit data error
Corrected data out
Copyright © 2012–2019, Texas Instruments Incorporated
SECDED
ECC[15:8]
Data[127:64]
SECDED
Data[63:0]
ECC[7:0]
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Flash
and
OTP
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