Epi Block Diagram; Functional Description - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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EPI Block Diagram

– 1 to 32 bits, FIFOed with speed control

– Useful for custom peripherals or for digital data acquisition and actuator controls

provides a block diagram of the EPI module.

The EPI controller provides a glueless, programmable interface to a variety of common external

peripherals such as SDRAM x16, Host Bus x8 and x16 devices, RAM, NOR Flash memory, CPLDs and

FPGAs. In addition, the EPI controller provides custom GPIO that can use a FIFO with speed control by

using either the internal write FIFO (WFIFO) or the non-blocking read FIFO (NBRFIFO). The WFIFO can

hold four words of data that are written to the external interface at the rate controlled by the EPI Main

Baud Rate (EPIBAUD) registers. The NBRFIFO can hold eight words of data and samples at the rate

controlled by the EPIBAUD register. The EPI controller provides predictable operation and thus has an

advantage over regular GPIO which has more variable timing due to on-chip bus arbitration and delays

across bus bridges. Blocking reads stall the CPU until the transaction completes. Non-blocking reads are

performed in the background and allow the processor to continue operation. In addition, write data can

also be stored in the WFIFO to allow multiple writes with no stalls.

NOTE: Both the WTAV bit field in the EPIWFIFOCNT register and the WBUSY bit in the EPISTAT

both of these bits are clear, then a new bus access may begin.

External Peripheral Interface (EPI)

Figure 17-1. EPI Block Diagram

SPRUH22I – April 2012 – Revised November 2019

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