M3 To C28 Core Ipc Acknowledge (Ctomipcack) Register; M3 To C28 Core Ipc Acknowledge (Ctomipcack) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

System Control Registers
Table 1-172. M3 to C28 Core Flag (MTOCIPCFLG) Register Field Descriptions (continued)
Bit Field
4 IPC5
3 IPC4
2 IPC3
1 IPC2
0 IPC1
1.13.11.4 C28 to M3 Core IPC Acknowledge (CTOMIPCACK) Register
Figure 1-161. M3 to C28 Core IPC Acknowledge (CTOMIPCACK) Register
31 30
IPC32 IPC31
W-0 W-0
23 22
IPC24 IPC23
W-0 W-0
15 14
IPC16 IPC15
W-0 W-0
7 6
IPC8 IPC7
W-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-173. M3 to C28 Core IPC Acknowledge (CTOMIPCACK) Register Field Descriptions
Bit Field
31 IPC32
30 IPC31
29 IPC30
28 IPC29
27 IPC28
26 IPC27
276
System Control and Interrupts
Value Description
0 MTOCIPCFLG Flag 5. M3 to C28 core IPC flag 5 status. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
0 MTOCIPCFLG Interrupt 4. M3 to C28 IPC interrupt 4 status flag. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
0 MTOCIPCFLG Interrupt 3. M3 to C28 IPC interrupt 3 status flag. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
0 MTOCIPCFLG Interrupt 2. M3 to C28 IPC interrupt 2 status flag. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
0 MTOCIPCFLG Interrupt 1. M3 to C28 IPC interrupt 1 status flag. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
29 28
IPC30 IPC29
W-0 W-0
21 20
IPC22 IPC21
W-0 W-0
13 12
IPC14 IPC13
W-0 W-0
5 4
IPC6 IPC5
W-0 W-0
Value Description
0 CTOMIPCACK Flag 32. C28 to M3 core IPC flag 32 acknowledge. Writing a '1' to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCACK Flag 31. C28 to M3 core IPC flag 31 acknowledge. Writing a '1' to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCACK Flag 30. C28 to M3 core IPC flag 30 acknowledge. Writing a '1' to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCACK Flag 29. C28 to M3 core IPC flag 29 acknowledge. Writing a '1' to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers
0 CTOMIPCACK Flag 28. C28 to M3 core IPC flag 28 acknowledge. Writing a '1' to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCACK Flag 27. C28 to M3 core IPC flag 27 acknowledge. Writing a '1' to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
Copyright © 2012–2019, Texas Instruments Incorporated
27 26
IPC28 IPC27
W-0 W-0
19 18
IPC20 IPC19
W-0 W-0
11 10
IPC12 IPC11
W-0 W-0
3 2
IPC4 IPC3
W-0 W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
25 24
IPC26 IPC25
W-0 W-0
17 16
IPC18 IPC17
W-0 W-0
9 8
IPC10 IPC9
W-0 W-0
1 0
IPC2 IPC1
W-0 W-0
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