Counter-Compare B Register (Cmpbm); Counter-Compare B Register (Cmpb); Counter-Compare A Mirror Register (Cmpam) Field Descriptions; Counter-Compare B Register (Cmpbm) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Registers
Table 7-42. Counter-Compare A Mirror Register (CMPAM) Field Descriptions
Bit Field
15-0 CMPA
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-43. Counter-Compare B Register (CMPBM) Field Descriptions
Bit Field
15-0 CMPB
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
746
C28 Enhanced Pulse Width Modulator (ePWM) Module
Value Description
0000-FFFFh CMPA and CMPAM can both be used to access the counter-compare A value. The only
difference is that the mirror register always reads back the active value.
By default writes to this register are shadowed. Unlike the CMPA register, reads of CMPAM
always return the active register value. Shadowing is enabled and disabled by the
CMPCTL[SHDWAMODE] bit.
• If CMPCTL[SHDWAMODE] = 0, then the shadow is enabled and any write will automatically
go to the shadow register. All reads will reflect the active register value. In this case, the
CMPCTL[LOADAMODE] bit field determines which event will load the active register from
the shadow register.
• Before a write, the CMPCTL[SHDWAFULL] bit can be read to determine if the shadow
register is currently full.
• If CMPCTL[SHDWAMODE] = 1, then the shadow register is disabled and any write will go
directly to the active register, that is the register actively controlling the hardware.
Figure 7-93. Counter-Compare B Register (CMPBM)
Value Description
0000-FFFFh CMPB and CMPBM can both be used to access the counter-compare A value. The only
difference is that the mirror register always reads back the active value.
By default writes to this register are shadowed. Unlike the CMPB register, reads of CMPBM
always return the active register value. Shadowing is enabled and disabled by the
CMPCTL[SHDWBMODE] bit.
• If CMPCTL[SHDWBMODE] = 0, then the shadow is enabled and any write will automatically
go to the shadow register. All reads will reflect the active register value. In this case, the
CMPCTL[LOADBMODE] bit field determines which event will load the active register from
the shadow register.
• Before a write, the CMPCTL[SHDWBFULL] bit can be read to determine if the shadow
register is currently full.
• If CMPCTL[SHDWBMODE] = 1, then the shadow register is disabled and any write will go
directly to the active register, that is the register actively controlling the hardware.
Figure 7-94. Counter-Compare B Register (CMPB)
Copyright © 2012–2019, Texas Instruments Incorporated
CMPB
R/W-0
CMPB
R/W-0
SPRUH22I – April 2012 – Revised November 2019
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