Flash Pump Semaphore; Mtocipc Message Registers; Ctomipc Message Registers - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Register Name
MTOCIPCCOM
MTOCIPCADDR
MTOCIPCDATAW
MTOCIPCDATAR
IPC Message registers that Control subsystem can use to convey a message to the master subsystem are
given in Table 1-37.
Register Name
CTOMIPCCOM
CTOMIPCADDR
CTOMIPCDATAW
CTOMIPCDATAR
Let us consider an example for the usage of these registers. The user's application might have a scenario
where the M3 requires knowing the data in one of the memories mapped to the C28x to which the M3
does not have read access. For this scenario, software can be designed such that:
1. When the M3 requires the data from C28x memory, the M3 should write a value of 0x0000007
(arbitrarily represents "16-bit data read" command) in the MTOCIPCCOM register and the address
where it wants the C28x to read data in the MTOCIPCADDR register.
2. After writing to these IPC message registers, the M3 should raise an IPC request using either an
MTOCIPC flag or interrupt.
3. When the C28x gets this IPC request from the M3, C28x software should be designed to read the
MTOCIPCCOM register and understand that the command value of 0x00000007 means 16-bit data
command.
4. Upon understanding the command, C28x software should read the MTOCIPCADDR register to get the
address that the M3 wrote.
5. Then the C28x software can read the data from that address and write the data that it obtained by
reading that memory location in MTOCIPCDATAR for the M3 to read.
In this way, user application can define the usage of the IPC message registers to accomplish mailbox
communications between the master and control subsystems.

1.12.7 Flash Pump Semaphore

There are two flash banks in this device. One flash bank is in the master subsystem and another flash
bank is in the control subsystem. The M3 core can erase, program, and read the master subsystem flash
bank, and the C28x core can erase, program, and read the control subsystem flash bank. But both of
these flash banks share a single flash pump for erase and program operations. Hence, only one core can
perform erase/program operations on its flash bank at any given time.
When the M3 core is performing erase/program operations on M3 flash bank, the C28x core cannot
erase/program the C28x flash bank, but the C28x core can execute code and/or read data from the C28x
flash bank. Similarly, when the C28x core is performing erase/program operations on the C28x flash bank,
the M3 core cannot erase/program the M3 flash bank, but the M3 core can execute code and/or read data
from the M3 flash bank.
SPRUH22I – April 2012 – Revised November 2019
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Table 1-36. MTOCIPC Message Registers
Description
MTOC IPC command register
MTOC IPC address register
MTOC IPC Data write register
MTOC IPC Data read register
Table 1-37. CTOMIPC Message Registers
Description
CTOM IPC command register
CTOM IPC address register
CTOM IPC Data write register
CTOM IPC Data read register
Copyright © 2012–2019, Texas Instruments Incorporated
Inter Processor Communications (IPC)
M3 Read/Write
Read/write
Read/write
Read/write
Read only
M3 Read/Write
Read/write
Read/write
Read/write
Read only
System Control and Interrupts
C28x Read/Write
Read only
Read only
Read only
Read/write
C28x Read/Write
Read only
Read only
Read only
Read/write
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