Table of Contents
Advertisement
www.ti.com
Table 17-39. EPI Host-Bus 16 Configuration 3 Register (EPIHB16CFG3) Field Descriptions (continued)
Bit
Field
16
BURST
15-8
Reserved
7-6
WRWS
5-2
Reserved
1-0
MODE
17.11.27 EPI Host-Bus 8 Configuration 4 (EPIHB8CFG4), offset 0x30C
NOTE: The MODE field in the EPICFG register configures whether EPI Host Bus mode is enabled.
For EPIHB8CFG4 to be valid, the MODE field must be 0x2.
Figure 17-54. EPI Host-Bus 8 Configuration 4 Register (EPIHB8CFG4) [offset 0x30C]
31
Reserved
R-0
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Value
Description
CS2 Burst Mode
Burst mode must be used with an ALE, which is configured by programming the CSCFG and
CSCFGEXT fields in the EPIHB16CFG2 register. Burst mode must be used in ADMUX, which is set
by the MODE field in EPIHB16CFG3.
Note: Burst mode is optimized for word-length accesses.
0
Burst mode is disabled
1
Burst mode is enabled for CS2
Reserved
CS2 Write Wait States
This field is used in conjunction with the EPIBAUD register.
This field adds wait states to the data phase of CS2 accesses (the address phase is not affected).
The effect is to delay the rising edge of WR (or the falling edge of WR). Each wait state adds two
EPI clock cycles to the access time. The WRWSM bit in the EPIHB16TIME3 register can decrease
the number of wait states by one EPI clock cycle for greater granularity. This field is used if the
CSBAUD bit is enabled in the EPIHB16CFG2 register. This field is not applicable in BURST mode.
0x0
Active WR is 2 EPI clocks
0x1
Active WR is 4 EPI clocks
0x2
Active WR is 6 EPI clocks
0x3
Active WR is 8 EPI clocks
Reserved
CS2 Host Bus Sub-Mode
This field determines which Host Bus 8 sub-mode to use for CS2 in multiple chip-select mode.
Sub-mode use is determined by the connected external peripheral. See
on how this bit field affects the operation of the EPI signals.
Note: The CSBAUD bit must be set to enable this CS2 MODE field. If CSBAUD is clear, all chip
selects use the MODE configuration defined in the EPIHB16CFG register.
0x0
ADMUX – AD[15:0]
Data and Address are muxed.
0x1
ADNONMUX – D[15:0]
Data and address are separate. This mode is not practical in HB16 mode for normal peripherals
because there are generally not enough address bits available.
0x2
Continuous Read - D[15:0]
This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OE
strobing. This mode is not practical in HB16 mode for normal SRAMs because there are generally
not enough address bits available.
0x3
Reserved
22
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
21
20
WRHIGH
RDHIGH
R/W-0
R/W-0
8
7
6
5
WRWS
RDWS
R/W-0
R/W-0
Register Descriptions
Table 17-7
for information
19
18
ALEHIGH
Reserved
R/W-1
R-0
4
3
2
1
Reserved
MODE
R-0
R/W-0
External Peripheral Interface (EPI)
16
0
1265
Advertisement
Chapters
Table of Contents
