Procedure For Configuring A Mcbsp For Spi Operation; Mcbsp As The Spi Master - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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15.7.5 Procedure for Configuring a McBSP for SPI Operation

To configure the McBSP for SPI master or slave operation:
Step 1. Place the transmitter and receiver in reset.
Clear the transmitter reset bit (XRST = 0) in SPCR2 to reset the transmitter. Clear the receiver reset bit
(RRST = 0) in SPCR1 to reset the receiver.
Step 2. Place the sample rate generator in reset.
Clear the sample rate generator reset bit (GRST = 0) in SPCR2 to reset the sample rate generator.
Step 3. Program registers that affect SPI operation.
Program the appropriate McBSP registers to configure the McBSP for proper operation as an SPI
master or an SPI slave. For a list of important bits settings, see one of the following topics:
•

McBSP as the SPI Master (

• McBSP as an SPI Slave (
Step 4. Enable the sample rate generator.
To release the sample rate generator from reset, set the sample rate generator reset bit (GRST = 1) in
SPCR2.
Make sure that during the write to SPCR2, you only modify GRST. Otherwise, you modify the McBSP
configuration you selected in the previous step.
Step 5. Enable the transmitter and receiver.
After the sample rate generator is released from reset, wait two sample rate generator clock periods for
the McBSP logic to stabilize.
If the CPU services the McBSP transmit and receive buffers, then you can immediately enable the
transmitter (XRST = 1 in SPCR2) and enable the receiver (RRST = 1 in SPCR1).
If the DMA controller services the McBSP transmit and receive buffers, then you must first configure
the DMA controller (this includes enabling the channels that service the McBSP buffers). When the
DMA controller is ready, make XRST = 1 and RRST = 1.
In either case, make sure you only change XRST and RRST when you write to SPCR2 and SPCR1.
Otherwise, you modify the bit settings you selected earlier in this procedure.
After the transmitter and receiver are released from reset, wait two sample rate generator clock periods
for the McBSP logic to stabilize.
Step 6. If necessary, enable the frame-synchronization logic of the sample rate generator.
After the required data acquisition setup is done (DXR[1,2] is loaded with data), set FRST = 1 if an
internally generated frame-synchronization pulse is required (that is, if the McBSP is the SPI master).
15.7.6 McBSP as the SPI Master
An SPI interface with the McBSP used as the master is shown in
configured as a master, the transmit output signal (DX) is used as the SIMO signal of the SPI protocol and
the receive input signal (DR) is used as the SOMI signal.
The register bit values required to configure the McBSP as a master are listed in
table are more details about the configuration requirements.
SPRUH22I – April 2012 – Revised November 2019
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Section 15.7.6)
Section 15.7.7)
Copyright © 2012–2019, Texas Instruments Incorporated
SPI Operation Using the Clock Stop Mode
Figure 15-41. When the McBSP is
Table
C28 Multichannel Buffered Serial Port (McBSP)
15-16. After the
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