Epi Sdram Configuration (Episdramcfg) Register, Offset 0X010; Epi Sdram Configuration (Episdramcfg) Register [Offset 0X010]; Epi Sdram Configuration (Episdramcfg) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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17.11.4 EPI SDRAM Configuration (EPISDRAMCFG) Register, offset 0x010

NOTE: The MODE field in the EPICFG register determines which configuration register is accessed
for offsets 0x010 and 0x014.
To access EPISDRAMCFG, the MODE field must be 0x1.
The SDRAM Configuration register is used to specify several parameters for the SDRAM controller. Note
that this register is reset when the MODE field in the EPICFG register is changed. If another mode is
selected and the SDRAM mode is selected again, the values must be reinitialized..
The SDRAM interface designed to interface to x16 SDRS DRAMs of 64 MHz or higher, with the address
and data pins overlapped (wire ORed on the board). See
Figure 17-31. EPI SDRAM Configuration (EPISDRAMCFG) Register [offset 0x010]
31 30 29
FREQ Reserved
R/W-0x1 R-0x0
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-17. EPI SDRAM Configuration (EPISDRAMCFG) Register Field Descriptions
Bit Field
31-30 FREQ
29-27 Reserved
26-16 RFSH
15-10 Reserved
9 SLEEP
8-2 Reserved
1-0 SIZE
SPRUH22I – April 2012 – Revised November 2019
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27 26
10 9
SLEEP
R/W-0
Value Description
Frequency Range
This field configures the frequency range used for delay references by internal counters. This EPI
frequency is the system frequency with the divider programmed by the COUNT0 bit in the
EPIBAUDn register bit. This field affects the power up, precharge, and auto refresh delays. This
field does not affect the refresh counting, which is configured separately using the RFSH field (and
is based on system clock rate and number of rows per bank). The ranges are:
0x0 0 - 15 MHz
0x1 15 - 30 MHz
0x2 30 - 50 MHz
0x3 50 - 100 MHz
Reserved
Refresh Counter
This field contains the refresh counter in system clocks. The reset value of 0x2EE provides a
refresh period of 64 ms when using a 50 MHz clock.
Reserved
Sleep Mode
0 No effect
1 The SDRAM is put into low power state, but is self-refreshed.
Reserved
Size of SDRAM
The value of this field affects address pins and behavior.
0x0 64 megabits (8MB)
0x1 128 megabits (16MB)
0x2 256 megabits (32MB)
0x3 512 megabits (64MB)
Copyright © 2012–2019, Texas Instruments Incorporated
Table 17-1 for pin assignments.
RFSH
R/W-0x2EE
8
Reserved
R-0
Register Descriptions
2 1
R/W-0
External Peripheral Interface (EPI)
16
0
SIZE
1231