Input Qualifier Clock Cycles - Texas Instruments Concerto F28M35 Series Technical Reference Manual

www.ti.com
GPIO Signal
1 1
SYSCLKOUT
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n
SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words,
the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. That would ensure 5 sampling periods for detection to occur. Since
external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Figure 4-41. Input Qualifier Clock Cycles
GPxQSELn = 1,0 (6 samples)
0 0 0 0 0 0
t
w(IQSW)
Sampling Window
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Copyright © 2012–2019, Texas Instruments Incorporated
C28 General-Purpose Input/Output (GPIO)
(A)
0 1 0 0 0 1
t Sampling Period determined
w(SP)
by GPxCTRL[QUALPRD]
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
General-Purpose Input/Output (GPIO)
1 1 1 1 1 1
(B)
(C)
)
1 1
383