Usb Pll Multiplier (Upllmult) Register; Usb Pll Configuration (Upllctl) Register Field Descriptions; Usb Pll Multiplier (Upllmult) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 1-109. USB PLL Configuration (UPLLCTL) Register Field Descriptions
Bit Field
31-3 Reserved
2 UPLLCLKEN
1 UPLLEN
0 UPLLCLKSRCSE
L

1.13.7.7 USB PLL Multiplier (UPLLMULT) Register

NOTE: Application must take care to program the USBPLLCR register in such a way that the output
clock is always 60 MHz. There is no clock divider after the USB PLL OUT.
31
15
Reserved
R-0:0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-110. USB PLL Multiplier (UPLLMULT) Register Field Descriptions
Bit Field
31-10 Reserved
9-8 UPLLFMULT
7-6 Reserved
SPRUH22I – April 2012 – Revised November 2019
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Value Description
Reserved
USB PLL Clock Enable
USB PLL bypassed or included in the USB clock path.
This bit decides if the USB PLL is bypassed to supply the 60-MHz clock to the USB
Note: The PLL bypass option can be used only with GPIO_XCLKIN as a clock source to the USB
because the oscillators will support only up to a 20 MHz input clock
0 USB PLL is bypassed; clock to the USB is direct feed from GPIO_XCLKIN.
1 USB PLL is on the clock path to USBCLK and it is the PLL multiplied clock.
USB PLL Enable
PLL enabled or disabled.
This bit decides if the USB PLL is enabled or not.
0 USB PLL is powered off and the clock to the USB is a direct feed from the input clock source as
decided by the USBPLLCLKSRCSEL bit.
1 USB PLL is enabled and the clock to the USB will depend on the USBPLLCR register configuration.
USB PLL Clock Source Select
This bit selects the source for the USB PLL input clock.
On XRS low and after XRS goes high, X1 is selected as clock source to the USB PLL by default.
The user would need to select X1 or GPIO_XCLKIN as the clock source during their initialization
process.
Whenever the user changes the clock source, using these bits, the USBPLLCR register will be
automatically forced to zero. This prevents potential PLL overshoot. The user will then have to write
to the USBPLLCR register to configure the appropriate divisor ratio.
0 X1 clock source is selected as clock to the USB PLL
1 GPIO_XCLKIN is selected as clock to the USB PLL
Figure 1-99. USB PLL Multiplier (UPLLMULT) Register
10 9
UPLLFMULT
R/W-0:0
Value Description
Reserved
USB PLL Fractional Multiplier
00 Fractional multiplier = 0
01 Fractional multiplier = 0.25
10 Fractional multiplier = 0.5
11 Fractional multiplier = 0.75
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0:0
8 7 6 5
Reserved
R-0:0
System Control Registers
UPLLIMULT
R/W-0
System Control and Interrupts
16
0
225