Tx & Rx Fifo Organization - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Functional Description
FIFO Word Read/Write
Sequence
1st
2nd
3rd
4th
5th to nth
last
(1)
If the CRC bit in the MACTCTL register is clear, the FCS bytes must be written with the correct CRC. If the CRC bit is set, the
Ethernet MAC automatically writes the FCS bytes.
19.3.1.3 Ethernet Transmission Options
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation by using
the DUPLEX bit in the MACTCTL register. Note that in 10BASE-T half-duplex mode, the transmitted data
is looped back on the receive path.
The Ethernet MAC automatically generates and inserts the Frame Check Sequence (FCS) at the end of
the transmit frame when the CRC bit in the MACTCTL register is set. However, for test purposes, this
feature can be disabled in order to generate a frame with an invalid CRC by clearing the CRC bit.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46 bytes.
The Ethernet MAC automatically pads the data section if the payload data section loaded into the FIFO is
less than the minimum 46 bytes when the PADEN bit in the MACTCTL register is set. This feature can be
disabled by clearing the PADEN bit.
The transmitter must be enabled by setting the TXEN bit in the MACTCTL register.
19.3.1.4 Ethernet Reception Options
The Ethernet MAC RX FIFO should be cleared during software initialization. The receiver should first be
disabled by clearing the RXEN bit in the Ethernet MAC Receive Control (MACRCTL) register, then the
FIFO can be cleared by setting the RSTFIFO bit in the MACRCTL register.
1384
M3 Ethernet Media Access Controller (EMAC)
Table 19-1. TX & RX FIFO Organization
Word Bit Fields
Data Length Least Significant
1:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
Copyright © 2012–2019, Texas Instruments Incorporated
TX FIFO (Write)
Byte
Data Length Most Significant
Byte
DA oct 1
DA oct 2
DA oct 3
DA oct 4
DA oct 5
DA oct 6
SA oct 1
SA oct 2
SA oct 3
SA oct 4
SA oct 5
SA oct 6
Len/Type Most Significant Byte
Len/Type Least Significant Byte
data oct n
data oct n + 1
data oct n + 2
data oct n + 3
FCS 1
FCS 2
FCS 3
FCS 4
SPRUH22I – April 2012 – Revised November 2019
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RX FIFO (Read)
Frame Length Least Significant
Byte
Frame Length Most Significant
Byte
(1)
(1)
(1)
(1)

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