Interrupt 32-63 Set Enable 1 (En1), Offset 0X104; Interrupt 64-95 Set Enable 2 (En2), Offset 0X108; Interrupt 96-127 Set Enable 3 (En3), Offset 0X10C; Interrupt 32-63 Set Enable 1 (En1) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

NVIC Register Descriptions

25.5.2 Interrupt 32-63 Set Enable 1 (EN1), offset 0x104

The Interrupt 32-63 Set Enable (EN1) register enables interrupts and shows which interrupts are enabled.
Bit 0 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. See the Cortex-M3 Processor chapter
for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not
enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates
the interrupt, regardless of its priority.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-12. Interrupt 32-63 Set Enable 1 (EN1) Register Field Descriptions
Bit Field
31-0 INT

25.5.3 Interrupt 64-95 Set Enable 2 (EN2), offset 0x108

The Interrupt 64-95 Set Enable (EN2) register enables interrupts and shows which interrupts are enabled.
Bit 0 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. See the Cortex-M3 Processor chapter
for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not
enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates
the interrupt, regardless of its priority.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-13. Interrupt 64-95 Set Enable 2 (EN2) Register Field Descriptions
Bit Field
31-0 INT

25.5.4 Interrupt 96-127 Set Enable 3 (EN3), offset 0x10C

The Interrupt 96-127 Set Enable (EN3) register enables interrupts and shows which interrupts are
enabled. Bit 0 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. See the Cortex-M3
Processor chapter for interrupt assignments.
1612
Cortex-M3 Peripherals
Figure 25-6. Interrupt 32-63 Set Enable 1 (EN1) Register
Value Description
Interrupt Enable
0 On a read, indicates the interrupt is disabled. On a write, no effect.
1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in the DIS1 register.
Figure 25-7. Interrupt 64-95 Set Enable 2 (EN2) Register
Value Description
Interrupt Enable
0 On a read, indicates the interrupt is disabled. On a write, no effect.
1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in the DIS2 register.
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INT
R/W-0
INT
R/W-0
SPRUH22I – April 2012 – Revised November 2019
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