Introduction; Features; Ssi Block Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Introduction

20.1 Introduction

Each SSI is a master or slave interface for synchronous serial communication with peripheral devices that

have either Freescale SPI, or Texas Instruments Synchronous Serial Interfaces.

The SSI module includes the following features:

Programmable interface operation for Freescale SPI, or Texas Instruments Synchronous Serial

Master or slave operation

Programmable clock bit rate and prescaler

Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep

Programmable data frame size from 4 to 16 bits

Internal loopback test mode for diagnostic/debug testing

Standard FIFO-based interrupts and End-of-Transmission interrupt

Efficient transfers using Micro Direct Memory Access Controller (µDMA)

– Separate channels for transmit and receive

– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO

contains four entries

– Transmit single request asserted when there is space in the FIFO; burst request asserted when

FIFO contains four or more entries are available to be written in the FIFO

– Maskable μDMA interrupts for receive and transmit complete

The SSI module block diagram is shown in the figure below.

M3 Synchronous Serial Interface (SSI)

SPRUH22I – April 2012 – Revised November 2019

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