Run Mode Clock Gating Control Register 0 (Rcgc0); Master Gpio High Performance Bus Control (Gpiohbctl) Register Field Descriptions; Run Mode Clock Gating Control Register 0 (Rcgc0) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

System Control Registers
Table 1-115. Master GPIO High Performance Bus Control (GPIOHBCTL) Register Field Descriptions
Bit Field
31-9 Reserved
8 PORT J
7 PORT H
6 PORT G
5 PORT F
4 PORT E
3 PORT D
2 PORT C
1 PORT B
0 PORT A

1.13.7.13 Run Mode Clock Gating Control Register 0 (RCGC0)

Figure 1-105. Run Mode Clock Gating Control Register 0 (RCGC0)
31 29 28 27
Reserved WDT1
R-0:0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-116. Run Mode Clock Gating Control Register 0 (RCGC0) Field Descriptions
Bit Field
31-29 Reserved
28 WDT1
27-4 Reserved
3 WDT0
228
System Control and Interrupts
Value Description
Reserved
PORT J AHB. This bit defines the memory aperture for Port J
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
PORT H AHB. This bit defines the memory aperture for Port H
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
PORT G AHB. This bit defines the memory aperture for Port G
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
PORT F AHB. This bit defines the memory aperture for Port F
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
PORT E AHB. This bit defines the memory aperture for Port E
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
PORT D AHB. This bit defines the memory aperture for Port D
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
PORT C AHB. This bit defines the memory aperture for Port C
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
PORT B AHB. This bit defines the memory aperture for Port B
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
PORT A AHB. This bit defines the memory aperture for Port A
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
Value Description
Reserved
WDT1 Clock Gating Control
This bit controls the clock gating for the WDT1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
WDT0 Clock Gating Control
This bit controls the clock gating for the WDT0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0:0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
4 3 2 0
WDT0 Reserved
R/W-0 R-0:0
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