Master-Transmitter/Receiver Bus Activity Defined By The Rm, Stt, And Stp Bits Of I2Cmdr; How The Mst And Fdf Bits Of I2Cmdr Affect The Role Of The Trx Bit Of I2Cmdr - Texas Instruments Concerto F28M35 Series Technical Reference Manual

I2C Module Registers
Table 14-5. I2C Mode Register (I2CMDR) Field Descriptions (continued)
Bit Field
2-0 BC
Table 14-6. Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of
RM STT
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
(1)
S = START condition; A = Address; D = Data byte; P = STOP condition;
Table 14-7. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR
MST FDF I2C Module State
0 0 In slave mode but not free data
format mode
0 1 In slave mode and free data
format mode
1 0 In master mode but not free data
format mode
1 1 In master mode and free data
format mode
1022
C28 Inter-Integrated Circuit Module
Value Description
Bit count bits. BC defines the number of bits (1 to 8) in the next data byte that is to be received or
transmitted by the I2C module. The number of bits selected with BC must match the data size of
the other device. Notice that when BC = 000b, a data byte has 8 bits. BC does not affect address
bytes, which always have 8 bits.
Note: If the bit count is less than 8, receive data is right-justified in I2CDRR(7-0), and the other bits
of I2CDRR(7-0) are undefined. Also, transmit data written to I2CDXR must be right-justified.
000 8 bits per data byte
001 1 bit per data byte
010 2 bits per data byte
011 3 bits per data byte
100 4 bits per data byte
101 5 bits per data byte
110 6 bits per data byte
111 7 bits per data byte
(1)
STP Bus Activity
0 None
1 P
0 S-A-D..(n)..D.
1 S-A-D..(n)..D-P
0 None
1 P
0 S-A-D-D-D.
1 None
Copyright © 2012–2019, Texas Instruments Incorporated
I2CMDR
Description
No activity
STOP condition
START condition, slave address, n data bytes (n = value in
I2CCNT)
START condition, slave address, n data bytes, STOP condition (n =
value in I2CCNT)
No activity
STOP condition
Repeat mode transfer: START condition, slave address, continuous
data transfers until STOP condition or next START condition
Reserved bit combination (No activity)
Function of TRX
TRX is a don't care. Depending on the command from the master, the I2C
module responds as a receiver or a transmitter.
The free data format mode requires that the I2C module remains the
transmitter or the receiver throughout the transfer. TRX identifies the role
of the I2C module:
TRX = 1: The I2C module is a transmitter.
TRX = 0: The I2C module is a receiver.
TRX = 1: The I2C module is a transmitter.
TRX = 0: The I2C module is a receiver.
TRX = 0: The I2C module is a receiver.
TRX = 1: The I2C module is a transmitter.
SPRUH22I – April 2012 – Revised November 2019
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