Usb External Power Control Interrupt Status And Clear Register (Usbepcisc), Offset 0X40C; Usb External Power Control Interrupt Status And Clear Register (Usbepcisc); Usb External Power Control Interrupt Status And Clear Register (Usbepcisc) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions

18.5.50 USB External Power Control Interrupt Status and Clear Register (USBEPCISC),

offset 0x40C
The USB external power control interrupt status and clear 32-bit register (USBEPCISC) specifies the
unmasked interrupt status of the two-pin external power interface.
Mode(s): OTG A or Host
USBEPCISC is shown in
Figure 18-61. USB External Power Control Interrupt Status and Clear Register (USBEPCISC)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field Value
31-1 Reserved 0
0 PF
0
1
1364
M3 Universal Serial Bus (USB) Controller
OTG B or Device
Figure 18-61 and described in
Reserved
R-0
Table 18-66. USB External Power Control Interrupt Status and
Clear Register (USBEPCISC) Field Descriptions
Description
Reserved. Reset is 0x0000.000.
USB Power Fault Interrupt Status and Clear.
This bit is cleared by writing a 1. Clearing this bit also clears the PF bit in the USBEPCISC register.
The PF bits in the USBEPCRIS and USBEPCIM registers are set, providing an interrupt to the interrupt
controller.
No interrupt has occurred or the interrupt is masked.
Copyright © 2012–2019, Texas Instruments Incorporated
Table 18-66.
SPRUH22I – April 2012 – Revised November 2019
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1 0
PF
R-0