Ethernet Mac Register Descriptions; Ethernet Mac Raw Interrupt Status/Acknowledge (Macris/Maciack) Register, Offset 0X000; Ethernet Mac Raw Interrupt Status/Acknowledge (Macris/Maciack) Register; Ethernet Mac Raw Interrupt Status/Acknowledge (Macris/Maciack) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Ethernet MAC Register Descriptions

19.6 Ethernet MAC Register Descriptions

The remainder of this section lists lists and describes the Ethernet MAC registers, in numerical order by

address offset. Also see

offset 0x000

The MACRIS/MACIACK register is the interrupt status and acknowledge register. On a read, this register

gives the current status value of the corresponding interrupt prior to masking. On a write, setting any bit

clears the corresponding interrupt status bit.

Figure 19-4. Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19-3. Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Register Field

M3 Ethernet Media Access Controller (EMAC)

Table 19-2. Ethernet Register Map (continued)

PHY Interrupt

No interrupt.

An enabled interrupt in the PHY layer has occurred. Check the appropriate PHY register to

determine the specific PHY event that triggered this interrupt.

This bit is cleared by writing a 1 to it.

MII Transaction Complete

No interrupt.

A transaction (read or write) on the MII interface has completed successfully.

This bit is cleared by writing a 1 to it.

Descriptions

SPRUH22I – April 2012 – Revised November 2019

Ethernet PHY Management

Ethernet PHYManagement

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Ethernet PHYManagement

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