RAM Control Module Registers
5.2.2.24 Master DMA Write Access Violation Address Register (MMDMAWRAVADDR)
Figure 5-39. Master DMA Write Access Violation Address Register (MMDMAWRAVADDR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-44. Master DMA Write Access Violation Address Register (CMDMAWRAVADDR) Field
Bit
Field
31-0
MDMAWRAVADDR
Figure 5-40. Master CPU Fetch Access Violation Address Register (MMFAVADDR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-45. Master CPU Fetch Access Violation Address Register (MMFAVADDR) Field
Bit
Field
31-0
MCPUFAVADDR
464
Internal Memory
NMDMAWRAVADDR
R-0
Descriptions
Value
Description
Master DMA Write Access Violation Address
This holds the address at which M3 µDMA attempted a write access and the master DMA
write access violation occurred.
MCPUFAVADDR
R-0
Descriptions
Value
Description
Master CPU Fetch Access Violation Address
This holds the address at which M3 CPU attempted a code fetch and the master CPU
fetch access violation occurred.
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SPRUH22I – April 2012 – Revised November 2019
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