Peripheral Clock Control Register 3 (Pclkcr3); Peripheral Clock Control Register 3 (Pclkcr3) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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1.13.7.30 Peripheral Clock Control Register 3 (PCLKCR3)

15
Reserved
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-133. Peripheral Clock Control Register 3 (PCLKCR3) Register Field Descriptions
Bit Field
15-12 Reserved
11 DMAENCLK
10-8 CPUTIMERnENC
LK
(n = 2-0)
7-0 Reserved
SPRUH22I – April 2012 – Revised November 2019
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Figure 1-122. Peripheral Clock Control Register 3 (PCLKCR3)
12
R-0
Value Description
Reserved
C28 DMA Clock Enable
When set, this enables the clock to the CPU timers on the C28 subsystem.
0 C28 DMA clock is disabled
1 C28 DMA clock is enabled
C28 CPU Timer 2-0 Clock Enables
When set, this enables the clock to the CPU timers on the C28 subsystem.
0 Timer clock is disabled
1 Timer clock is enabled
Reserved
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11 10
DMAENCLK CPUTIMER2ENCL
K
R/W-0 R/W-1
Reserved
R-0:0
System Control Registers
9 8
CPUTIMER1ENCL CPUTIMER0ENCL
K K
R/W-1 R/W-1
0
System Control and Interrupts
245