Register Map; External Peripheral Interface (Epi) Register Map M3 Base Address: 0X400D_0000, C28X Base Address: 0X7C00 - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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17.10 Register Map

Table 17-11
lists the EPI registers. The offset listed is a hexadecimal increment to the register's address,
relative to the base address of 0x400D.0000 (ending address of 0x400D.0FFF). Note that the EPI
controller clock must be enabled before the registers can be programmed. There must be a delay of three
system clocks after the EPI module clock is enabled before any EPI module registers are accessed.
NOTE: A back-to-back write followed by a read of the same register reads the value that written by
the first write access, not the value from the second write access. (This situation only occurs
when the processor core attempts this action, the µDMA does not do this.) To read back
what was just written, another instruction must be generated between the write and read.
Read-write does not have this issue, so use of read-write for clear of error interrupt cause is
not affected.
For all versions of EPI, only WORD read and write accesses to registers are supported.
M3 Offset
Address
0x000
0x004
0x010
0x010
0x010
0x010
0x014
0x014
0x014
0x01C
0x020
0x024
0x028
0x030
0x034
0x038
0x060
0x06C
0x070
0x074
0x078
SPRUH22I – April 2012 – Revised November 2019
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Table 17-11. External Peripheral Interface (EPI) Register Map
M3 Base Address: 0x400D_0000, C28x Base Address: 0x7C00
C28x Offset Address
Acronym
0x000
0x002
EPIBAUD
0x008
EPISDRAMCFG
0x008
EPIHB8CFG
0x008
EPIHB16CFG
0x008
EPIGPCFG
0x00A
EPIHB8CFG2
0x00A
EPIHB16CFG2
0x00A
EPIGPCFG2
0x00E
EPIADDRMAP
0x010
EPIRSIZE0
0x012
EPIRADDR0
0x014
EPIRPSTD0
0x018
EPIRSIZE1
0x01A
EPIRADDR1
0x01C
EPIRPSTD1
0x030
0x036
EPIRFIFOCNT
0x038
EPIREADFIFO
0x03A
EPIREADFIFO1
0x03C
EPIREADFIFO2
Copyright © 2012–2019, Texas Instruments Incorporated
Type
EPICFG
R/W
0x0000.0000
R/W
0x0000.0000
R/W
0x42EE.0000
R/W
0x0000.0000
R/W
0x0000.0000
R/W
0x0000.0000
R/W
0x0000.0000
R/W
0x0000.0000
R/W
0x0000.0000
R/W
0x0000.0000
R/W
0x0000.0000
R/W
0x0000.0000
R/W
0x0000.0000
R/W
0x0000.0003
R/W
0x0000.0000
R/W
0x0000.0000
EPISTAT
R
0x0000.0000
R
R
R
R
Register Map
Reset
Description
EPI Configuration Register
EPI Main Baud Rate
Register
EPI SDRAM Configuration
Register
EPI Host-Bus 8
Configuration Register
EPI Host-Bus 16
Configuration Register
EPI General-Purpose
Configuration Register
EPI Host-Bus 8
Configuration 2 Register
EPI Host-Bus 16
Configuration 2 Register
EPI General-Purpose
Configuration 2 Register
EPI Address Map Register
EPI Read Size 0 Register
EPI Read Address 0
Register
EPI Non-Blocking Read Data
0 Register
EPI Read Size 1 Register
EPI Read Address 1
Register
EPI Non-Blocking Read Data
1 Register
EPI Status Register
EPI Read FIFO Count
-
Register
-
EPI Read FIFO Register
EPI Read FIFO Alias 1
-
Register
EPI Read FIFO Alias 2
-
Register
External Peripheral Interface (EPI)
1225

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