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R8C/18 Group, R8C/19 Group
15.2
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows data transmission and reception after setting the desired bit rate and transfer
data format. Table 15.4 lists the UART Mode Specifications. Table 15.5 lists the Registers Used and
Settings for UART Mode.
Table 15.4
UART Mode Specifications
Item
Transfer data format
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
i = 0 to 1
NOTE:
1. If an overrun error occurs, the contents of the UiRB register will be undefined. The IR bit in the SiRIC
register remains unchanged.
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
• Character bit (transfer data): Selectable among 7, 8, or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bit: Selectable among 1 or 2 bits
• CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n+1))
fj = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
• CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
fEXT: input from CLKi pin n = value set in UiBRG register: 00h to FFh
• Before transmission starts, the following are required.
- TE bit in UiC1 register is set to 1 (transmission enabled).
- TI bit in UiC1 register is set to 0 (data in UiTB register).
• Before reception starts, the following are required.
- RE bit in UiC1 register is set to 1 (reception enabled).
- Start bit deleted
• When transmitting, one of the following conditions can be selected.
- UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit register
(when transmit starts).
- UiIRS bit is set to 1 (transfer ends):
When serial interface completes transmitting data from the UARTi
transmit register.
• When receiving
When transferring data from the UARTi receive register to UiRB register
(when receive ends).
(1)
• Overrun error
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receives the bit preceding the final
stop bit of the next data item.
• Framing error
This error occurs when the set number of stop bits is not detected.
• Parity error
This error occurs when parity is enabled, and the number of 1's in parity
and character bits do not match the number of 1's set.
• Error sum flag
This flag is set is set to 1 when an overrun, framing, or parity error is
generated.
Page 157 of 233
Specification
15. Serial Interface
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