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M16C/64A Group
23.3.2
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows data to be transmitted/received after setting the desired bit rate and bit order.
Table 23.9 lists the UART Mode Specifications.
Table 23.9
UART Mode Specifications
Item
Data format
Transmit/receive clock
Transmit/receive control Selectable from CTS , RTS , or CTS / RTS function disabled
Transmission start
conditions
Reception start
conditions
Interrupt request
generation timing
Error detection
Selectable functions
i = 0 to 2, 5 to 7
Note:
1.
If an overrun error occurs, the receive data of the UiRB register will be undefined. The IR bit in the SiRIC register
remains unchanged.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
•
Character bit: selectable from 7, 8, or 9 bits
•
Start bit: 1 bit
•
Parity bit: selectable from odd, even, or none
•
Stop bit: selectable from 1 bit or 2 bits
•
The CKDIR bit in the UiMR register = 0 (internal clock):
fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
•
CKDIR bit = 1 (external clock):
fEXT: Input from CLKi pin n: Setting value of UiBRG register 00h to FFh
To start transmission, satisfy the following requirements:
•
The TE bit in the UiC1 register is 1 (transmission enabled)
•
The TI bit in the UiC1 register is 0 (data present in the UiTB register)
If CTS function is selected, input on the CTSi pin = low
•
To start reception, satisfy the following requirements:
•
The RE bit in the UiC1 register is 1 (reception enabled)
•
Start bit detection
For transmission, one of the following conditions can be selected:
•
The UiIRS bit in the UiC1 or UCON register is 0 (transmit buffer empty):
When transferring data from the UiTB register to the UARTi transmit register (at start of
transmission)
•
The UiIRS bit is 1 (transmission completed):
When the serial interface completes sending data from the UARTi transmit register
For reception:
•
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
•
(1)
Overrun error
This error occurs if the serial interface starts receiving the next unit of data before reading
the UiRB register and receives the bit before the last stop bit of the next unit of data.
•
Framing error
This error occurs when the number of stop bits set is not detected.
•
Parity error
This error occurs when the number of 1's of the parity bit and character bit does not match
the set value of the PRY bit in the UiMR register.
•
Error sum flag
This flag becomes 1 when any of the overrun, framing, or parity errors occur.
•
LSB first, MSB first selection
Whether to start transmitting/receiving the data from bit 0 or from bit 7 can be selected.
•
Serial data logic switch
This function inverts the logic of the transmit/receive data. The start and stop bits are not
inverted.
•
TXD, RXD I/O polarity switch
This function inverts the polarities of the TXD pin output and RXD pin input. The logic
levels of all I/O data are inverted.
Separate CTS / RTS pins (UART0)
•
CTS0 and RTS0 are input/output from separate pins.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Specification
------------------------ -
16 n
fEXT
------------------------ -
(
)
16 n
+
1
fj
(
)
+
1
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