Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1390

ADSP-SC58x MSI Register Descriptions
Interrupt Mask Register
The register provides bits that allow the masking of unwanted interrupts.
MSI_IMSK
EBE (R/W)
End-bit Error (Read)/Write no CRC
ACD (R/W)
Auto Command Done
SBEBCI (R/W)
Start Bit Error(SBE)/Busy Complete
Interrupt (BCI)
HLE (R/W)
Hardware Locked Write Error
FRUN (R/W)
FIFO Underrun/Overrun Error
HTO (R/W)
Data Starvation by Host Timeout
DRTO (R/W)
Data Read Timeout
RTO (R/W)
Response Timeout
SDIOMSK0 (R/W)
SDIO Interrupt Mask for SDIO Device 0
Figure 26-33: MSI_IMSK Register Diagram
Table 26-36: MSI_IMSK Register Fields
Bit No.
(Access)
31:16 SDIOMSK0
(R/W)
15 EBE
(R/W)
26–84
15 14 13 12 11
0 0 0 0 0
31 30 29 28 27
0 0 0 0 0
Bit Name
SDIO Interrupt Mask for SDIO Device 0.
The MSI_IMSK.SDIOMSK0 bits mask SDIO interrupts, one bit for one card.
When masked, SDIO interrupt detection for that card is disabled. A 0 masks an inter-
rupt, and 1 enables an interrupt.
End-bit Error (Read)/Write no CRC.
The MSI_IMSK.EBE bit masks the end bit read/write no CRC error.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
10 9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
26 25 24 23 22 21 20 19
0 0 0 0 0 0 0 0
Description/Enumeration
0 Masked
1 Enabled
2 1 0
0 0 0
CD (R/W)
Card Detect
RE (R/W)
Response Error
CMDDONE (R/W)
Command Done
DTO (R/W)
Data Transfer Over
TXDR (R/W)
Transmit FIFO Data Request
RXDR (R/W)
Receive FIFO Data Request
RCRC (R/W)
Response CRC Error
DCRC (R/W)
Data CRC Error
18 17 16
0 0 0