STMicroelectronics SPC572L series Reference Manual page 1182

Deserial Serial Peripheral Interface (DSPI)
46.5.2.3 FIFO Disable operation
The FIFO Disable mechanisms allow SPI transfers without using the TX FIFO, CMD FIFO
or RX FIFO.
The DSPI operates as a double-buffered simplified SPI when the FIFOs are disabled.
The Transmit and Receive side of the FIFOs are disabled separately:
•
MCR[DIS_TXF] disables TX FIFO and CMD FIFO.
–
–
•
MCR[DIS_RXF] bit disables the RX FIFO.
–
–
The FIFO Disable mechanisms are transparent to the user and to host software. Transmit
data and commands are written to the PUSHR and received data is read from the POPR.
46.5.2.4 Transmit First In First Out (TX FIFO) buffering mechanism
The TX FIFO functions as a buffer of SPI data for transmission.
The TX FIFO holds 4 words, each consisting of SPI data that is added to the TX FIFO by
writing to the Data field of DSPI PUSH FIFO Register (PUSHR).
The number of entries in the TX FIFO is device-specific.
TX FIFO entries can only be removed from the TX FIFO by being shifted out or by flushing
the TX FIFO.
The TX FIFO Counter field (TXCTR) in the DSPI Status Register (SR) indicates the number
of valid entries in the TX FIFO. TXCTR is updated every time an 8 or 16-bit write takes place
to the Data field of DSPI_PUSHR or SPI data is transferred into the shift register from the
TX FIFO.
The TXNXTPTR field indicates which TX FIFO Entry will be transmitted during the next
transfer. This field is incremented every time SPI data is transferred from the TX FIFO to the
shift register. The maximum value of the field is equal to the maximum implemented TXFR
register number and it rolls over after reaching the maximum.
The TXFRn Registers are invalid in Extended SPI Mode as TX FIFO and CMD FIFO are
used separately.
46.5.2.4.1 Filling the TX FIFO
Host software or other intelligent blocks can add (push) entries to the TX FIFO and CMD
FIFO by writing to the PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) in
the SR is set.When TX FIFO is full and the DMA controller indicates that a write to PUSHR
is complete, the TFFF bit is cleared. Writing a '1' to the TFFF bit also clears it. The DSPI
ignores attempts to push data to a full TX FIFO; the state of the TX FIFO does not change
and no error condition is indicated.
The TFFF can generate a DMA request or an interrupt request. See
Transmit FIFO Fill interrupt or DMA request
1182/2058
TFFF, TFUF, CMDFFF, CMDCTR and TXCTR fields in the status register and the
extended status register behave as if there is a one-entry FIFO.
The contents of the TXFR registers and TXNXTPTR and CMDNXTPTR are
undefined.
The RFDF, RFOF and RXCTR fields in the status register behave as if there is a
one-entry FIFO.
The contents of the RXFR registers and POPNXTPTR are undefined.
DocID027809 Rev 4
for details.
RM0400
Section 46.5.12.2: