STMicroelectronics SPC572L series Reference Manual page 1145

RM0400
Field
Disable Transmit FIFO
When the TX FIFO is disabled, the transmit part of the DSPI (TXFIFO and CMD FIFO) operates
18 as a simplified double-buffered SPI.
DIS_TXF This bit can only be written when the MDIS bit is cleared.
0 Tx FIFO is enabled.
1 Tx FIFO is disabled.
Disable Receive FIFO
When the RX FIFO is disabled, the receive part of the DSPI operates as a simplified double-
19 buffered SPI.
DIS_RXF This bit can only be written when the MDIS bit is cleared.
0 Rx FIFO is enabled.
1 Rx FIFO is disabled.
Clear TX FIFO
Flushes TX FIFO and CMD FIFO. Writing a '1' to CLR_TXF clears the TX FIFO and CMD FIFO
20
Counters. The CLR_TXF bit is always read as zero.
CLR_TXF
0 Do not clear the Tx FIFO and CMD FIFO counters.
1 Clears the Tx FIFO and CMD FIFO counters.
Clear RX FIFO
Flushes RX FIFO. Writing a '1' to CLR_RXF clears the RX Counter. The CLR_RXF bit is always
21
read as zero.
CLR_RXF
0 Do not clear the Rx FIFO counter.
1 Clear the Rx FIFO counter.
Sample Point
Controls when the DSPI master samples SIN in Modified Transfer Format.
This field is valid only when CPHA bit in CTAR is 0.
22–23
00 0 protocol clocks between SCK edge and SIN sample
SMPL_PT
01 1 protocol clock between SCK edge and SIN sample
10 2 protocol clocks between SCK edge and SIN sample
11 Reserved
24–27
This read-only bitfield is reserved and always has the value zero.
Reserved
Extended SPI Mode
Enables use of CTARE (Command and Transfer Attribute Register Extended) Registers, which
allow the user to send up to 32-bit SPI frames.
Command Cycling is also enabled, allowing the user to send multiple Data Frames in a single
28
Command Frame.
XSPI
When MCR[DIS_TXF] is asserted, Extended SPI Mode cannot be used to transmit SPI frames
over 16 bits in size.
0 Normal SPI Mode. Up to 16-bit Frames. Command Cycling is not available.
1 Extended SPI Mode. Up to 32-bit SPI Frames. Command Cycling Enabled
Table 610. DSPI_MCR field descriptions(Continued)
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
Description
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