STMicroelectronics SPC572L series Reference Manual page 1406

SENT Receiver (SRX)
detected, after which all checks are automatically enabled. This is done to avoid multiple
assertions of the interrupt to CPU in case the channel become unstable and send wrong
data continuously.
49.4.7.1 Calibration pulse length check
The calibration pulse length check happens in conjunction with Clock Compensation Logic
since current calibration pulse is detected in this block. The Clock Compensation Logic
detects a calibration pulse of length between 42 and 70 tick counts. This check will assert
the CAL_LEN_ERR status bit on failure.
49.4.7.2 Successive calibration pulse check
The successive calibration pulse check checks if successive calibration pulses differ by >
+1.5625% (1/64) or < -1.5625%. The accuracy of this check will depend on the frequency of
the protocol clock used. Specifically, the higher the frequency, the closer the check will be to
1.5625%. So if protocol clock is T
will be of 1.5625% ± {100 × (4 × T
clock of a channel by 1.5625% - {100 × (4 × T
assert the CAL_DIAG_ERR status bit on failure.
When Option 2 of successive calibration pulse check is enabled, the CAL_RESYNC bit will
be asserted on every third successive error detected by this check.
49.4.7.3 Not the expected number of edges check
The number of negative edges between two successive calibration pulses is counted and
compared with expected number of edges in case of preferred option of successive
calibration pulse check. The expected number of nibbles is the sum of following:
•
Status and Communication nibble (1 No.)
•
Data nibbles (Programmable as per user software)
•
CRC nibble (1 No.)
•
Pause Pulse, if configured (1 No.)
This check ("Not the expected number of edges check") will assert the NUM_EDGES_ERR
status bit on failure. The check does not run when Option 2 (low latency) of successive
calibration pulse check is enabled. This check is not masked after any other error is
detected so it could be redundant if it is flagged along with CAL_DIAG_ERR and
CAL_LEN_ERR. However, this is true only when CPU is clearing error status bits as and
when they are asserted. If errors are accumulated, the above cannot be deduced.
49.4.7.4 Nibble value check
As part of this check, the lengths of the following nibbles are checked to remain in between
0 and 15 ticks:
• Status and Communication nibble
•
all Data nibbles
•
CRC nibble
The nibble value check will assert the NIB_VAL_ERR status bit on failure. This error can be
flagged along with NUM_EDGES_ERR in which case the former can be ignored as the
number of pulses in the message is incorrect. However, this is true only when CPU is
1406/2058
and channel tick period is T
HF_CLK
) / (42 × T
HF_CLK TX_CLK
HF_CLK
DocID027809 Rev 4
TX_CLK
)}. So it won't allow variance in
) / (42 × T
)}. This check will
TX_CLK
RM0400
then the check